Design area utilization seems misleading

[TanjIsGray]

I realized that size of my designs is not matching "design area" reported. On the GUI view I can see my design uses a rectangular space of around 24 um2 (not including the halo) but

finish report_design_area
Design area 15 u^2 60% utilization.

was in the log. So, that seems to mean that the macros placed totaled 15 um2 of space but packed into 24 um2 of silicon. It is useful to know both numbers but I think the size of the space inside the halo is more practical to know. It certainly seems that space would be the most likely expectation for the meaning of "design area".

Just calling attention to this. Not a bug, but users could be easily misled about what it means.

[rovinski]

This is standard terminology.
"Design area": total area consumed by instances.
"Core area": total area in which instances can be placed.
"Die area": the total area of the chip.
Die area >= core area >= design area. Design area utilization (the 60% in the above) is also always expressed as (design area)/(core area)

[maliberty]

By 'halo' do you mean the area between the core and the die area?

[TanjIsGray]

Yes.