RTLMP_FLOW=True and HIREARCHICAL_SYNTHESIS=1

[oharboe]

Why are these used in combination?

What happens if I don't?

#4529 has an fMax of 125, which isn't enormously impressive. There are 79 levels of logic in the longest path, which indicates to me that something isn't being optimized in synthesis...

BOOMv documents that it relies heavily on register retiming and I've also observed that it needs register cloning for synchronous reset.

Hence, I want to try disabling hierarchical synthesis on MegaBoom, but given the long turnaround times, 40 hours, it would be nice to know a little bit about what I'm doing and what I should expect...

[rovinski]

I believe that RTLMP requires hierarchy in the netlist to work at all. If the netlist is flat, RTLMP won't work.

[oharboe]

Hold off on that until I have some numbers as to whether it is faster :-)

[oharboe]

The techmap stage is the one that takes the most time, it seems.

I wouldn't expect there to be any area estimates before techmap, but perhaps even before techmap there is some number(not really area) that is good 'nuf to drive the policy and yield the same quality of results?

[oharboe]

RTLMP fails on MegaBoom without hierarchical synthesis: #4539

[oharboe]

The running times of The-OpenROAD-Project/OpenROAD-flow-scripts#1755 are almost the same as today, so this didn't pan out immediately. Without technology map, which takes a lot of time, there's no area estimate.

[oharboe]

@maliberty Tinkered a bit with it... The-OpenROAD-Project/OpenROAD-flow-scripts#1758

[oharboe]

At least no public tests. We would have to run the private ones as well.

[gadfort]

@oharboe the retiming doesn't work in Yosys (and not in OpenROAD), so that is going to be a limitation. We ran into this as well with something else from the Chisel team folks and there isn't a good solution at the moment

[oharboe]

I see. I'm thinking, for now, retiming has to be done manually in the RTL (Chisel for MegaBoom).

What about register cloning, is that done in yosys?

My main effort currently is to get MegaBoom running nicely in a Bazel layer on top of ORFS, but I'm walking past all sorts of rabbitholes... Bazel offers artifacts and much more fine grained dependencies than ORFS.

[gadfort]

register cloning is something that is driven by physically aware constraints, so you really wouldn't want yosys to do that. For retiming that would require a more fundamental change to how yosys and abc interface to eachother and see if abc supports retiming

[oharboe]

I see. At least with flattening the registers in the synchronous reset aren't hidden inside the top module. I can see how register retiming and cloning would have to be more explicit in the RTL for now. Yes, it's abstraction leakage, but for now, it is what it is.

[maliberty]

fwiw abc does have a retime command

retime – Implements several flavors of retiming: most forward, most backward, a [minimum-register](http://www.eecs.berkeley.edu/~alanmi/publications/2007/fmcad07_min.pdf), a heuristic minimum-delay, the delay-optimal retiming presented in Peichen Pan, “Continuous retiming: algorithms and applications”, ICCD 1997, pp. 116-121. The latches are optimally shared across the fanout stems when the circuit is transformed from the sequential AIG into a logic network. The computation of initial states after retiming is reduced to a SAT problem, which is solved using [MiniSat](http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/). The known issues include non-verifies after retiming with latches, which have don’t-care initial states. (For the time being, don’t-care initial states can be replaced by fixed initial states using command init.)

https://people.eecs.berkeley.edu/~alanmi/abc/

[gadfort]

@maliberty that is good to know. I was wondering about that when talking with @precisionmoon earlier