From 3a3b3968e3b47430eed0c989fdb9946120a277c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 19 Nov 2024 13:18:53 +0100 Subject: [PATCH] megaboom: branch predictors as macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- BUILD.bazel | 42 +++++++++++++++++++++++++++++++++++++++- constraints-boomtile.sdc | 18 ++++++++++++++++- pdn.tcl | 35 +++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 2 deletions(-) create mode 100644 pdn.tcl diff --git a/BUILD.bazel b/BUILD.bazel index 3851ae8..d172965 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -377,6 +377,16 @@ SWEEP = { }, "stage_sources": {"floorplan": ["write_macro_placement"]}, }, + "1": { + "description": "Hierarchical, branch predictors as macros", + "variables": { + "HOLD_SLACK_MARGIN": "-900", + "PDN_TCL": "$(location :pdn.tcl)", + "MAX_ROUTING_LAYER": "M9", + }, + "macros": ["ComposedBranchPredictorBank_generate_abstract"], + "stage_sources": {"floorplan": ["pdn.tcl"]}, + }, } BOOMTILE_VARIABLES = SKIP_REPORT_METRICS | FAST_BUILD_SETTINGS | { @@ -428,6 +438,36 @@ boomtile_all_rams = boom_regfile_rams.keys() + all_srams.keys() ALL_VARIANTS = SWEEP | OTHER_VARIANTS +BRANCH_PREDICTOR_VARIABLES = SKIP_REPORT_METRICS | FAST_BUILD_SETTINGS | { + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", + "IO_CONSTRAINTS": "$(location :io-boomtile)", + "PLACE_DENSITY": "0.24", + # We only need hierarchical synthesis when we are running through floorplan + # write_macro_placement macros.tcl + "SYNTH_HIERARCHICAL": "1", + "SDC_FILE": "$(location :constraints-boomtile)", + "MACRO_PLACE_HALO": "4 4", + "PLACE_PINS_ARGS": "-annealing", + "DIE_AREA": "0 0 300 400", + "CORE_AREA": "0 0 298 398", + # Saves hours of build time, specific to BoomTile + "SKIP_LAST_GASP": "1", + "SETUP_SLACK_MARGIN": "-1300", + "HOLD_SLACK_MARGIN": "-200", +} + +orfs_flow( + name = "ComposedBranchPredictorBank", + abstract_stage = "cts", + arguments = BRANCH_PREDICTOR_VARIABLES, + macros = [ + ":" + m + "_generate_abstract" + for m in boomtile_all_rams + ], + stage_sources = BOOMTILE_SOURCES, + verilog_files = all_source_files, +) + [orfs_flow( name = "BoomTile", arguments = BOOMTILE_VARIABLES | ALL_VARIANTS[variant].get("variables", {}), @@ -435,7 +475,7 @@ ALL_VARIANTS = SWEEP | OTHER_VARIANTS ":" + m + "_generate_abstract" for m in boomtile_all_rams if m not in ALL_VARIANTS[variant].get("dissolve", []) - ], + ] + ALL_VARIANTS[variant].get("macros", []), previous_stage = ALL_VARIANTS[variant].get("previous_stage", {}), renamed_inputs = ALL_VARIANTS[variant].get("renamed_inputs", {}), # Explictily set arguments for a stage when stages are not listed in diff --git a/constraints-boomtile.sdc b/constraints-boomtile.sdc index a0c10d0..838d1ab 100644 --- a/constraints-boomtile.sdc +++ b/constraints-boomtile.sdc @@ -11,4 +11,20 @@ set clk_port_name clock # Ignore synchronous reset for now. set_false_path -from [get_ports reset] -source $env(PLATFORM_DIR)/constraints.sdc +set clk_port [get_ports $clk_port_name] +create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port + +set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +if {[llength [all_registers]] > 0} { + set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] + set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] + set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] + + group_path -name in2reg -from $non_clk_inputs -to [all_registers] + group_path -name reg2out -from [all_registers] -to [all_outputs] + group_path -name reg2reg -from [all_registers] -to [all_registers] +} + +set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] +group_path -name in2out -from $non_clk_inputs -to [all_outputs] diff --git a/pdn.tcl b/pdn.tcl new file mode 100644 index 0000000..c146615 --- /dev/null +++ b/pdn.tcl @@ -0,0 +1,35 @@ +# based on ORFS/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl, +# but added power higher up + +#################################### +# global connections +#################################### +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + +#################################### +# voltage domains +#################################### +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +#################################### +# standard cell grid +# M1 M2 are for follow pin, width derived from PG rail in standard cell +# M5 stripe width rerived from one of width allowed in LEF, offset and pitch +# put stripe on M5 track +# M4 M5 ring follow stripe width +#################################### +define_pdn_grid -name {top} -voltage_domains {CORE} + +add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} + +add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins + +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring + +add_pdn_connect -grid {top} -layers {M1 M2} +add_pdn_connect -grid {top} -layers {M2 M5} +add_pdn_connect -grid {top} -layers {M4 M5} +# allow routing at all metal levels +add_pdn_connect -grid {top} -layers {M5 M9}