SystemVerilog.tmLanguage

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					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
					<key>3</key>
					<dict>
						<key>name</key>
						<string>entity.name.type.class.systemverilog</string>
					</dict>
				</dict>
				<key>match</key>
				<string>\b(virtual\s+)?(class)\s+\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
				<key>name</key>
				<string>meta.definition.class.systemverilog</string>
			</dict>
			<dict>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>entity.other.inherited-class.systemverilog</string>
					</dict>
				</dict>
				<key>match</key>
				<string>\b(extends)\s+([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
				<key>name</key>
				<string>meta.definition.systemverilog</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#all-types</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#operators</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#port-dir</string>
			</dict>
			<dict>
				<key>match</key>
				<string>\b(and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\b</string>
				<key>name</key>
				<string>support.type.systemverilog</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#strings</string>
			</dict>
			<dict>
				<key>match</key>
				<string>\$\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
				<key>name</key>
				<string>support.function.systemverilog</string>
			</dict>
			<!-- Cast operator -->
			<dict>
				<key>match</key>
				<string>\b([a-zA-Z_][a-zA-Z0-9_]*)(')(?=\()</string>
				<key>name</key>
				<string>meta.cast.systemverilog</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>storage.type.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.cast.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<!-- Parameter/localparameter with no type in uppercase -->
			<dict>
				<key>match</key>
				<string>^\s*(localparam|parameter)\s+([A-Z_][A-Z0-9_]*)\b\s*(?=(=))</string>
				<key>name</key>
				<string>meta.param.systemverilog</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.other.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>constant.other.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<!-- Parameter/localparameter with no type -->
			<dict>
				<key>match</key>
				<string>^\s*(localparam|parameter)\s+([a-zA-Z_][a-zA-Z0-9_]*)\b\s*(?=(=))</string>
				<key>name</key>
				<string>meta.param.systemverilog</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.other.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<!-- Variable/Parameter/localparameter with user-defined type -->
			<dict>
				<key>match</key>
				<string>^\s*(local\s+|protected\s+|localparam\s+|parameter\s+)?(const\s+|virtual\s+)?(rand\s+|randc\s+)?(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)\b\s*(?=(#\s*\([\w,]+\)\s*)?([a-zA-Z][a-zA-Z0-9_\s\[\]']*)(;|,|=|'\{))</string>
				<key>name</key>
				<string>meta.userdefined.systemverilog</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.other.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.other.systemverilog</string>
					</dict>
					<key>3</key>
					<dict>
						<key>name</key>
						<string>storage.type.rand.systemverilog</string>
					</dict>
					<key>5</key>
					<dict>
						<key>name</key>
						<string>support.type.scope.systemverilog</string>
					</dict>
					<key>6</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.scope.systemverilog</string>
					</dict>
					<key>7</key>
					<dict>
						<key>name</key>
						<string>storage.type.userdefined.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<dict>
				<key>match</key>
				<string>\s*\b(option)\.</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.cover.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<dict>
				<key>match</key>
				<string>\s*\b(local|const|protected|virtual|localparam|parameter)\b</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.other.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<dict>
				<key>match</key>
				<string>\s*\b(rand|randc)\b</string>
				<key>name</key>
				<string>storage.type.rand.systemverilog</string>
			</dict>
			<!-- Module instantiation with parameter -->
			<dict>
				<key>begin</key>
				<string>^(\s*(bind)\s+([a-zA-Z_][\w\.]*))?\s*([a-zA-Z_][a-zA-Z0-9_]*)\s*(?=#[^#])</string>
				<key>beginCaptures</key>
				<dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
					<key>4</key>
					<dict>
						<key>name</key>
						<string>storage.module.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>(?=;|=|:)</string>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#module-binding</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#module-param</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b([a-zA-Z_][a-zA-Z0-9_]*)\b(?=\s*(\(|$))</string>
						<key>name</key>
						<string>entity.name.type.module.systemverilog</string>
					</dict>
				</array>
				<key>name</key>
				<string>meta.module.inst.param.systemverilog</string>
			</dict>
			<!-- Module instantiation with no param -->
			<dict>
				<key>begin</key>
				<string>\b([a-zA-Z_][a-zA-Z0-9_]*)\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\s*(\[(\d+)(\:(\d+))?\])?\s*(\(|$)</string>
				<key>beginCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>storage.module.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>entity.name.type.module.systemverilog</string>
					</dict>
					<key>4</key>
					<dict>
						<key>name</key>
						<string>constant.numeric.systemverilog</string>
					</dict>
					<key>6</key>
					<dict>
						<key>name</key>
						<string>constant.numeric.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>;</string>
				<!-- <string>;|=|,|$</string> -->
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#module-binding</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
				</array>
				<key>name</key>
				<string>meta.module.inst.systemverilog</string>
			</dict>
			<!-- Struct assignement (could also match array assignment) -->
			<dict>
				<key>name</key>
				<string>meta.struct.assign.systemverilog</string>
				<key>begin</key>
				<string>\b\s+(&lt;?=)\s*(\'{)</string>
				<key>beginCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.other.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.other.systemverilog</string>
					</dict>
					<key>3</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.other.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>;</string>
				<key>patterns</key>
				<array>
					<dict>
						<key>match</key>
						<string>\b(\w+)\s*(:)(?!:)</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>support.function.field.systemverilog</string>
							</dict>
							<key>2</key>
							<dict>
								<key>name</key>
								<string>keyword.operator.other.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#storage-scope-systemverilog</string>
					</dict>
				</array>
			</dict>
			<dict>
				<key>include</key>
				<string>#storage-scope-systemverilog</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#functions</string>
			</dict>
			<dict>
				<key>include</key>
				<string>#constants</string>
			</dict>
		</array>
		<key>repository</key>
		<dict>
			<key>functions</key>
			<dict>
				<key>match</key>
				<string>\b(\w+)(?=\s*\()</string>
				<key>name</key>
				<string>support.function.generic.systemverilog</string>
			</dict>
			<key>all-types</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#storage-type-systemverilog</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#storage-modifier-systemverilog</string>
					</dict>
					<!-- <dict>
						<key>include</key>
						<string>#const-modifier-systemverilog</string>
					</dict> -->
				</array>
			</dict>
			<key>constants</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>match</key>
						<string>(\b\d+)?'(s?[bB]\s*[0-1xXzZ?][0-1_xXzZ?]*|s?[oO]\s*[0-7xXzZ?][0-7_xXzZ?]*|s?[dD]\s*[0-9xXzZ?][0-9_xXzZ?]*|s?[hH]\s*[0-9a-fA-FxXzZ?][0-9a-fA-F_xXzZ?]*)((e|E)(\+|-)?[0-9]+)?(?!'|\w)</string>
						<key>name</key>
						<string>constant.numeric.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>'[01xXzZ]</string>
						<key>name</key>
						<string>constant.numeric.bit.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b((\d[\d_]*)(e|E)(\+|-)?[0-9]+)\b</string>
						<key>name</key>
						<string>constant.numeric.exp.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b(\d[\d_]*)\b</string>
						<key>name</key>
						<string>constant.numeric.decimal.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b(\d+(fs|ps|ns|us|ms|s)?)\b</string>
						<key>name</key>
						<string>constant.numeric.time.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b([A-Z][A-Z0-9_]*)\b</string>
						<key>name</key>
						<string>constant.other.net.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>(`ifdef|`ifndef|`default_nettype)\s+(\w+)</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>constant.other.preprocessor.systemverilog</string>
							</dict>
							<key>2</key>
							<dict>
								<key>name</key>
								<string>support.variable.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<dict>
						<key>match</key>
						<string>`(celldefine|else|elsif|endcelldefine|endif|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef|begin_\w+|end_\w+|remove_\w+|restore_\w+)\b</string>
						<key>name</key>
						<string>constant.other.preprocessor.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>`\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
						<key>name</key>
						<string>constant.other.define.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b(null)\b</string>
						<key>name</key>
						<string>support.constant.systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>operators</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>match</key>
						<string>(=|==|===|!=|!==|&lt;=|&gt;=|&lt;|&gt;)</string>
						<key>name</key>
						<string>keyword.operator.comparison.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>(\-|\+|\*|\/|%)</string>
						<key>name</key>
						<string>keyword.operator.arithmetic.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>(!|&amp;&amp;|\|\||\bor\b)</string>
						<key>name</key>
						<string>keyword.operator.logical.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>(&amp;|\||\^|~|{|'{|}|&lt;&lt;|&gt;&gt;|\?|:)</string>
						<key>name</key>
						<string>keyword.operator.bitwise.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>(#|@)</string>
						<key>name</key>
						<string>keyword.operator.other.systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>comments</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>begin</key>
						<string>/\*</string>
						<key>captures</key>
						<dict>
							<key>0</key>
							<dict>
								<key>name</key>
								<string>punctuation.definition.comment.systemverilog</string>
							</dict>
						</dict>
						<key>end</key>
						<string>\*/</string>
						<key>name</key>
						<string>comment.block.systemverilog</string>
					</dict>
					<dict>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>punctuation.definition.comment.systemverilog</string>
							</dict>
						</dict>
						<key>match</key>
						<string>(//).*$\n?</string>
						<key>name</key>
						<string>comment.line.double-slash.systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>port-dir</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<!-- Match ports with size declarations -->
						<key>match</key>
						<string>\s*\b(output|input|inout|ref)\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\s+(?=\[[a-zA-Z0-9_\-\+]*:[a-zA-Z0-9_\-\+]*\]\s+[a-zA-Z_][a-zA-Z0-9_\s]*)</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>support.type.systemverilog</string>
							</dict>
							<key>3</key>
							<dict>
								<key>name</key>
								<string>support.type.scope.systemverilog</string>
							</dict>
							<key>4</key>
							<dict>
								<key>name</key>
								<string>keyword.operator.scope.systemverilog</string>
							</dict>
							<key>5</key>
							<dict>
								<key>name</key>
								<string>storage.type.interface.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<!-- Match ports without size declarations -->
					<dict>
						<key>match</key>
						<string>\s*\b(output|input|inout|ref)\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\s+(?=[a-zA-Z_][a-zA-Z0-9_\s]*)</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>support.type.systemverilog</string>
							</dict>
							<key>3</key>
							<dict>
								<key>name</key>
								<string>support.type.scope.systemverilog</string>
							</dict>
							<key>4</key>
							<dict>
								<key>name</key>
								<string>keyword.operator.scope.systemverilog</string>
							</dict>
							<key>5</key>
							<dict>
								<key>name</key>
								<string>storage.type.interface.systemverilog</string>
							</dict>
						</dict>
					</dict>

					<dict>
						<key>match</key>
						<string>\s*\b(output|input|inout|ref)\b</string>
						<key>name</key>
						<string>support.type.systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>base-grammar</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#all-types</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<!-- Signals with user-defined type -->
					<dict>
						<key>match</key>
						<string>^\s*([a-zA-Z_][a-zA-Z0-9_]*)\s+[a-zA-Z_][a-zA-Z0-9_,=\s]*</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>storage.type.interface.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<dict>
						<key>include</key>
						<string>#storage-scope-systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>storage-type-systemverilog</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>match</key>
						<string>\s*\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\b</string>
						<key>name</key>
						<string>storage.type.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\s*\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\b</string>
						<key>name</key>
						<string>storage.type.uvm.systemverilog</string>
					</dict>
				</array>
			</dict>
			<key>storage-scope-systemverilog</key>
			<dict>
				<key>match</key>
				<string>\b([a-zA-Z_][a-zA-Z0-9_]*)(::)</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>support.type.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.scope.systemverilog</string>
					</dict>
				</dict>
				<key>name</key>
				<string>meta.scope.systemverilog</string>
			</dict>
			<key>storage-modifier-systemverilog</key>
			<dict>
				<key>match</key>
				<string>\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\b</string>
				<key>name</key>
				<string>storage.modifier.systemverilog</string>
			</dict>
			<!-- <key>const-modifier-systemverilog</key>
			<dict>
				<key>match</key>
				<string>\s*\bconst\b</string>
				<key>name</key>
				<string>keyword.other.systemverilog</string>
			</dict> -->
			<!-- Interface with modport declaration -->
			<key>ifmodport</key>
			<dict>
				<key>match</key>
				<string>\b([a-zA-Z_][a-zA-Z0-9_]*)\.([a-zA-Z_][a-zA-Z0-9_]*)\s+([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>storage.type.interface.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>support.modport.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<key>strings</key>
			<dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>begin</key>
						<string>"</string>
						<key>beginCaptures</key>
						<dict>
							<key>0</key>
							<dict>
								<key>name</key>
								<string>punctuation.definition.string.begin.systemverilog</string>
							</dict>
						</dict>
						<key>end</key>
						<string>"</string>
						<key>endCaptures</key>
						<dict>
							<key>0</key>
							<dict>
								<key>name</key>
								<string>punctuation.definition.string.end.systemverilog</string>
							</dict>
						</dict>
						<key>name</key>
						<string>string.quoted.double.systemverilog</string>
						<key>patterns</key>
						<array>
							<dict>
								<key>match</key>
								<string>\\.</string>
								<key>name</key>
								<string>constant.character.escape.systemverilog</string>
							</dict>
							<dict>
								<key>match</key>
								<string>(?x)%
										(\d+\$)?                             # field (argument #)
										[#0\- +']*                           # flags
										[,;:_]?                              # separator character (AltiVec)
										((-?\d+)|\*(-?\d+\$)?)?              # minimum field width
										(\.((-?\d+)|\*(-?\d+\$)?)?)?         # precision
										(hh|h|ll|l|j|t|z|q|L|vh|vl|v|hv|hl)? # length modifier
										[bdiouxXhHDOUeEfFgGaACcSspnmt%]      # conversion type
									</string>
								<key>name</key>
								<string>constant.other.placeholder.systemverilog</string>
							</dict>
							<dict>
								<key>match</key>
								<string>%</string>
								<key>name</key>
								<string>invalid.illegal.placeholder.systemverilog</string>
							</dict>
						</array>
					</dict>
				</array>
			</dict>
			<key>module-binding</key>
			<dict>
				<key>begin</key>
				<string>\.([a-zA-Z_][a-zA-Z0-9_]*)\s*\(</string>
				<key>beginCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>support.function.port.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>\)</string>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b([a-zA-Z_]\w*)(::)</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>support.type.scope.systemverilog</string>
							</dict>
							<key>2</key>
							<dict>
								<key>name</key>
								<string>keyword.operator.scope.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<dict>
						<key>match</key>
						<string>\b([a-zA-Z_]\w*)(')</string>
						<key>captures</key>
						<dict>
							<key>1</key>
							<dict>
								<key>name</key>
								<string>storage.type.interface.systemverilog</string>
							</dict>
							<key>2</key>
							<dict>
								<key>name</key>
								<string>keyword.operator.cast.systemverilog</string>
							</dict>
						</dict>
					</dict>
					<dict>
						<key>match</key>
						<string>\$\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
						<key>name</key>
						<string>support.function.systemverilog</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b(virtual)\b</string>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
				</array>
				<key>match</key>
				<string>\.([a-zA-Z_][a-zA-Z0-9_]*)\s*</string>
				<key>captures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>support.function.port.implicit.systemverilog</string>
					</dict>
				</dict>
			</dict>
			<key>module-param</key>
			<dict>
				<key>name</key>
				<string>meta.module-param.systemverilog</string>
				<key>begin</key>
				<string>(#)\s*\(</string>
				<key>beginCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.param.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>\)</string>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#comments</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#constants</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#operators</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#strings</string>
					</dict>
					<dict>
						<key>include</key>
						<string>#module-binding</string>
					</dict>
					<dict>
						<key>match</key>
						<string>\b(virtual)\b</string>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
				</array>
			</dict>
			<!-- Anonymous struct/union-->
			<key>struct-anonymous</key>
			<dict>
				<key>begin</key>
				<string>\s*\b(struct|union)\s*(packed)?\s*</string>
				<key>beginCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
					<key>2</key>
					<dict>
						<key>name</key>
						<string>keyword.control.systemverilog</string>
					</dict>
				</dict>
				<key>end</key>
				<string>(})\s*([a-zA-Z_]\w*)\s*;</string>
				<key>endCaptures</key>
				<dict>
					<key>1</key>
					<dict>
						<key>name</key>
						<string>keyword.operator.other.systemverilog</string>
					</dict>
				</dict>
				<key>patterns</key>
				<array>
					<dict>
						<key>include</key>
						<string>#base-grammar</string>
					</dict>
				</array>
				<key>name</key>
				<string>meta.struct.anonymous.systemverilog</string>
			</dict>
		</dict>
		<key>scopeName</key>
		<string>source.systemverilog</string>
		<key>uuid</key>
		<string>789be04c-8b74-352e-8f37-63d336001277</string>
	</dict>
</plist>