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diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt
index 5aecb48..058af73 100644
--- a/Documentation/networking/ip-sysctl.txt
+++ b/Documentation/networking/ip-sysctl.txt
@@ -22,6 +22,13 @@ ip_no_pmtu_disc - BOOLEAN
min_pmtu - INTEGER
default 552 - minimum discovered Path MTU
+fwmark_reflect - BOOLEAN
+ Controls the fwmark of kernel-generated IPv4 reply packets that are not
+ associated with a socket for example, TCP RSTs or ICMP echo replies).
+ If unset, these packets have a fwmark of zero. If set, they have the
+ fwmark of the packet they are replying to.
+ Default: 0
+
route/max_size - INTEGER
Maximum number of routes allowed in the kernel. Increase
this when using large numbers of interfaces and/or routes.
@@ -1048,6 +1055,13 @@ proxy_ndp - INTEGER
2 NDP packets are sent to userspace, where a userspace proxy
can be implemented
+fwmark_reflect - BOOLEAN
+ Controls the fwmark of kernel-generated IPv6 reply packets that are not
+ associated with a socket for example, TCP RSTs or ICMPv6 echo replies).
+ If unset, these packets have a fwmark of zero. If set, they have the
+ fwmark of the packet they are replying to.
+ Default: 0
+
conf/interface/*:
Change special settings per interface.
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 9dd4347..b95ba4d 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -39,6 +39,7 @@
#include <linux/percpu.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
+#include <linux/wakeup_reason.h>
#include <asm/irq.h>
#include <asm/exception.h>
@@ -257,6 +258,7 @@ static void gic_show_resume_irq(struct gic_chip_data *gic)
i = find_next_bit(pending, gic->max_irq, i+1)) {
pr_warning("%s: %d triggered", __func__,
i + gic->irq_offset);
+ log_wakeup_reason(i + gic->irq_offset);
}
}
diff --git a/arch/arm/configs/Glitch_flo_defconfig b/arch/arm/configs/Glitch_flo_defconfig
index 31d49d7..327c0e4 100644
--- a/arch/arm/configs/Glitch_flo_defconfig
+++ b/arch/arm/configs/Glitch_flo_defconfig
@@ -2784,7 +2784,6 @@ CONFIG_MSM_KGSL_PAGE_TABLE_SIZE=0xFFF0000
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_MSM_KGSL_MMU_PAGE_FAULT=y
# CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES is not set
-# CONFIG_MSM_KGSL_SIMPLE_GOV is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
@@ -3587,7 +3586,15 @@ CONFIG_RTC_INTF_ALARM_DEV=y
CONFIG_RTC_DRV_PM8XXX=y
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
+CONFIG_UIO=y
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+CONFIG_UIO_MSM_SHAREDMEM=y
#
# Virtio drivers
@@ -3874,7 +3881,6 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
CONFIG_DYNAMIC_FSYNC=y
-CONFIG_RESTRICT_ROOTFS_SLAVE=y
#
# Kernel hacking
diff --git a/arch/arm/configs/flo_defconfig b/arch/arm/configs/flo_defconfig
index d9ef152..82e75a9 100644
--- a/arch/arm/configs/flo_defconfig
+++ b/arch/arm/configs/flo_defconfig
@@ -487,11 +487,12 @@ CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ASHMEM=y
-CONFIG_ANDROID_LOGGER=y
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
diff --git a/arch/arm/mach-msm/asustek/flo/board-flo-storage.c b/arch/arm/mach-msm/asustek/flo/board-flo-storage.c
index 4113334..8f25e1f 100644
--- a/arch/arm/mach-msm/asustek/flo/board-flo-storage.c
+++ b/arch/arm/mach-msm/asustek/flo/board-flo-storage.c
@@ -332,8 +332,10 @@ static struct mmc_platform_data *apq8064_sdc4_pdata;
void __init apq8064_init_mmc(void)
{
- if (apq8064_sdc1_pdata)
+ if (apq8064_sdc1_pdata) {
apq8064_add_sdcc(1, apq8064_sdc1_pdata);
+ apq8064_add_uio();
+ }
if (apq8064_sdc2_pdata)
apq8064_add_sdcc(2, apq8064_sdc2_pdata);
diff --git a/arch/arm/mach-msm/asustek/flo/board-flo.h b/arch/arm/mach-msm/asustek/flo/board-flo.h
index dc8f322..a46efca 100644
--- a/arch/arm/mach-msm/asustek/flo/board-flo.h
+++ b/arch/arm/mach-msm/asustek/flo/board-flo.h
@@ -78,6 +78,7 @@ extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1;
struct mmc_platform_data;
int __init apq8064_add_sdcc(unsigned int controller,
struct mmc_platform_data *plat);
+int __init apq8064_add_uio(void);
void apq8064_init_mmc(void);
void apq8064_init_gpiomux(void);
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index 6f71492..0819424 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -332,8 +332,10 @@ static struct mmc_platform_data *apq8064_sdc4_pdata;
void __init apq8064_init_mmc(void)
{
- if (apq8064_sdc1_pdata)
+ if (apq8064_sdc1_pdata) {
apq8064_add_sdcc(1, apq8064_sdc1_pdata);
+ apq8064_add_uio();
+ }
if (apq8064_sdc2_pdata)
apq8064_add_sdcc(2, apq8064_sdc2_pdata);
diff --git a/arch/arm/mach-msm/board-8064.h b/arch/arm/mach-msm/board-8064.h
index 256fac9..cab700d 100644
--- a/arch/arm/mach-msm/board-8064.h
+++ b/arch/arm/mach-msm/board-8064.h
@@ -78,6 +78,7 @@ extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1;
struct mmc_platform_data;
int __init apq8064_add_sdcc(unsigned int controller,
struct mmc_platform_data *plat);
+int __init apq8064_add_uio(void);
void apq8064_init_mmc(void);
void apq8064_init_gpiomux(void);
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index a17621f..9fa7360 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -1680,6 +1680,30 @@ int __init apq8064_add_sdcc(unsigned int controller,
return platform_device_register(pdev);
}
+#define MSM_UIO_RMTFS_BASE 0x8FF00000
+#define MSM_UIO_RMTFS_END (MSM_UIO_RMTFS_BASE + 0x40000)
+
+static struct resource msm_device_uio_rmtfs_rsc[] = {
+ {
+ .name = "rmtfs",
+ .flags = IORESOURCE_MEM,
+ .start = MSM_UIO_RMTFS_BASE,
+ .end = MSM_UIO_RMTFS_END - 1,
+ },
+};
+
+struct platform_device apq8064_device_uio_rmtfs = {
+ .name = "msm_sharedmem",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(msm_device_uio_rmtfs_rsc),
+ .resource = msm_device_uio_rmtfs_rsc,
+};
+
+int __init apq8064_add_uio(void)
+{
+ return platform_device_register(&apq8064_device_uio_rmtfs);
+}
+
static struct resource resources_sps[] = {
{
.name = "pipe_mem",
diff --git a/arch/arm/mach-msm/msm_kcal_ctrl.c b/arch/arm/mach-msm/msm_kcal_ctrl.c
index fbcd77d..c523cef 100644
--- a/arch/arm/mach-msm/msm_kcal_ctrl.c
+++ b/arch/arm/mach-msm/msm_kcal_ctrl.c
@@ -569,11 +569,7 @@ int __init kcal_ctrl_init(void)
kcalPtr->refresh_display = kcal_refresh_values;
#endif
- unsigned int addr;
-
- addr = kallsyms_lookup_name("update_preset_lcdc_lut");
- *(funcPtr *)addr = (funcPtr)update_lcdc_lut;
-
+
platform_add_devices(msm_panel_devices,
ARRAY_SIZE(msm_panel_devices));
diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c
index 1a9a6a5..665fb47 100644
--- a/drivers/cpufreq/cpufreq_stats.c
+++ b/drivers/cpufreq/cpufreq_stats.c
@@ -20,6 +20,8 @@
#include <linux/kobject.h>
#include <linux/spinlock.h>
#include <linux/notifier.h>
+#include <linux/sort.h>
+#include <linux/err.h>
#include <asm/cputime.h>
static spinlock_t cpufreq_stats_lock;
@@ -44,6 +46,20 @@ struct cpufreq_stats {
#endif
};
+struct all_cpufreq_stats {
+ unsigned int state_num;
+ cputime64_t *time_in_state;
+ unsigned int *freq_table;
+};
+
+struct all_freq_table {
+ unsigned int *freq_table;
+ unsigned int table_size;
+};
+
+static struct all_freq_table *all_freq_table;
+
+static DEFINE_PER_CPU(struct all_cpufreq_stats *, all_cpufreq_stats);
static DEFINE_PER_CPU(struct cpufreq_stats *, cpufreq_stats_table);
struct cpufreq_stats_attribute {
@@ -54,14 +70,24 @@ struct cpufreq_stats_attribute {
static int cpufreq_stats_update(unsigned int cpu)
{
struct cpufreq_stats *stat;
+ struct all_cpufreq_stats *all_stat;
unsigned long long cur_time;
cur_time = get_jiffies_64();
spin_lock(&cpufreq_stats_lock);
stat = per_cpu(cpufreq_stats_table, cpu);
- if (stat->time_in_state)
+ all_stat = per_cpu(all_cpufreq_stats, cpu);
+ if (!stat) {
+ spin_unlock(&cpufreq_stats_lock);
+ return 0;
+ }
+ if (stat->time_in_state) {
stat->time_in_state[stat->last_index] +=
cur_time - stat->last_time;
+ if (all_stat)
+ all_stat->time_in_state[stat->last_index] +=
+ cur_time - stat->last_time;
+ }
stat->last_time = cur_time;
spin_unlock(&cpufreq_stats_lock);
return 0;
@@ -92,6 +118,62 @@ static ssize_t show_time_in_state(struct cpufreq_policy *policy, char *buf)
return len;
}
+static int get_index_all_cpufreq_stat(struct all_cpufreq_stats *all_stat,
+ unsigned int freq)
+{
+ int i;
+ if (!all_stat)
+ return -1;
+ for (i = 0; i < all_stat->state_num; i++) {
+ if (all_stat->freq_table[i] == freq)
+ return i;
+ }
+ return -1;
+}
+
+static ssize_t show_all_time_in_state(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ ssize_t len = 0;
+ unsigned int i, cpu, freq, index;
+ struct all_cpufreq_stats *all_stat;
+ struct cpufreq_policy *policy;
+
+ len += scnprintf(buf + len, PAGE_SIZE - len, "freq\t\t");
+ for_each_possible_cpu(cpu) {
+ len += scnprintf(buf + len, PAGE_SIZE - len, "cpu%d\t\t", cpu);
+ if (cpu_online(cpu))
+ cpufreq_stats_update(cpu);
+ }
+
+ if (!all_freq_table)
+ goto out;
+ for (i = 0; i < all_freq_table->table_size; i++) {
+ freq = all_freq_table->freq_table[i];
+ len += scnprintf(buf + len, PAGE_SIZE - len, "\n%u\t\t", freq);
+ for_each_possible_cpu(cpu) {
+ policy = cpufreq_cpu_get(cpu);
+ if (policy == NULL)
+ continue;
+ all_stat = per_cpu(all_cpufreq_stats, policy->cpu);
+ index = get_index_all_cpufreq_stat(all_stat, freq);
+ if (index != -1) {
+ len += scnprintf(buf + len, PAGE_SIZE - len,
+ "%llu\t\t", (unsigned long long)
+ cputime64_to_clock_t(all_stat->time_in_state[index]));
+ } else {
+ len += scnprintf(buf + len, PAGE_SIZE - len,
+ "N/A\t\t");
+ }
+ cpufreq_cpu_put(policy);
+ }
+ }
+
+out:
+ len += scnprintf(buf + len, PAGE_SIZE - len, "\n");
+ return len;
+}
+
#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf)
{
@@ -155,6 +237,9 @@ static struct attribute_group stats_attr_group = {
.name = "stats"
};
+static struct kobj_attribute _attr_all_time_in_state = __ATTR(all_time_in_state,
+ 0444, show_all_time_in_state, NULL);
+
static int freq_table_get_index(struct cpufreq_stats *stat, unsigned int freq)
{
int index;
@@ -189,6 +274,29 @@ static void cpufreq_stats_free_sysfs(unsigned int cpu)
cpufreq_cpu_put(policy);
}
+static void cpufreq_allstats_free(void)
+{
+ int i;
+ struct all_cpufreq_stats *all_stat;
+
+ sysfs_remove_file(cpufreq_global_kobject,
+ &_attr_all_time_in_state.attr);
+
+ for (i = 0; i < total_cpus; i++) {
+ all_stat = per_cpu(all_cpufreq_stats, i);
+ if (!all_stat)
+ continue;
+ kfree(all_stat->time_in_state);
+ kfree(all_stat);
+ per_cpu(all_cpufreq_stats, i) = NULL;
+ }
+ if (all_freq_table) {
+ kfree(all_freq_table->freq_table);
+ kfree(all_freq_table);
+ all_freq_table = NULL;
+ }
+}
+
static int cpufreq_stats_create_table(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table)
{
@@ -262,6 +370,106 @@ error_get_fail:
return ret;
}
+static int compare_for_sort(const void *lhs_ptr, const void *rhs_ptr)
+{
+ unsigned int lhs = *(const unsigned int *)(lhs_ptr);
+ unsigned int rhs = *(const unsigned int *)(rhs_ptr);
+ if (lhs < rhs)
+ return -1;
+ if (lhs > rhs)
+ return 1;
+ return 0;
+}
+
+static bool check_all_freq_table(unsigned int freq)
+{
+ int i;
+ for (i = 0; i < all_freq_table->table_size; i++) {
+ if (freq == all_freq_table->freq_table[i])
+ return true;
+ }
+ return false;
+}
+
+static void create_all_freq_table(void)
+{
+ all_freq_table = kzalloc(sizeof(struct all_freq_table),
+ GFP_KERNEL);
+ if (!all_freq_table)
+ pr_warn("could not allocate memory for all_freq_table\n");
+ return;
+}
+
+static void add_all_freq_table(unsigned int freq)
+{
+ unsigned int size;
+ size = sizeof(unsigned int) * (all_freq_table->table_size + 1);
+ all_freq_table->freq_table = krealloc(all_freq_table->freq_table,
+ size, GFP_ATOMIC);
+ if (IS_ERR(all_freq_table->freq_table)) {
+ pr_warn("Could not reallocate memory for freq_table\n");
+ all_freq_table->freq_table = NULL;
+ return;
+ }
+ all_freq_table->freq_table[all_freq_table->table_size++] = freq;
+}
+
+static void cpufreq_allstats_create(unsigned int cpu)
+{
+ int i , j = 0;
+ unsigned int alloc_size, count = 0;
+ struct cpufreq_frequency_table *table = cpufreq_frequency_get_table(cpu);
+ struct all_cpufreq_stats *all_stat;
+ bool sort_needed = false;
+
+ if (!table)
+ return;
+
+ for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+ unsigned int freq = table[i].frequency;
+ if (freq == CPUFREQ_ENTRY_INVALID)
+ continue;
+ count++;
+ }
+
+ all_stat = kzalloc(sizeof(struct all_cpufreq_stats),
+ GFP_KERNEL);
+ if (!all_stat) {
+ pr_warn("Cannot allocate memory for cpufreq stats\n");
+ return;
+ }
+
+ /*Allocate memory for freq table per cpu as well as clockticks per freq*/
+ alloc_size = count * sizeof(int) + count * sizeof(cputime64_t);
+ all_stat->time_in_state = kzalloc(alloc_size, GFP_KERNEL);
+ if (!all_stat->time_in_state) {
+ pr_warn("Cannot allocate memory for cpufreq time_in_state\n");
+ kfree(all_stat);
+ all_stat = NULL;
+ return;
+ }
+ all_stat->freq_table = (unsigned int *)
+ (all_stat->time_in_state + count);
+
+ spin_lock(&cpufreq_stats_lock);
+ for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+ unsigned int freq = table[i].frequency;
+ if (freq == CPUFREQ_ENTRY_INVALID)
+ continue;
+ all_stat->freq_table[j++] = freq;
+ if (all_freq_table && !check_all_freq_table(freq)) {
+ add_all_freq_table(freq);
+ sort_needed = true;
+ }
+ }
+ if (sort_needed)
+ sort(all_freq_table->freq_table, all_freq_table->table_size,
+ sizeof(unsigned int), &compare_for_sort, NULL);
+ all_stat->state_num = j;
+ per_cpu(all_cpufreq_stats, cpu) = all_stat;
+ spin_unlock(&cpufreq_stats_lock);
+}
+
static int cpufreq_stat_notifier_policy(struct notifier_block *nb,
unsigned long val, void *data)
{
@@ -274,6 +482,10 @@ static int cpufreq_stat_notifier_policy(struct notifier_block *nb,
table = cpufreq_frequency_get_table(cpu);
if (!table)
return 0;
+
+ if (!per_cpu(all_cpufreq_stats, cpu))
+ cpufreq_allstats_create(cpu);
+
ret = cpufreq_stats_create_table(policy, table);
if (ret)
return ret;
@@ -330,6 +542,9 @@ static int cpufreq_stats_create_table_cpu(unsigned int cpu)
if (!table)
goto out;
+ if (!per_cpu(all_cpufreq_stats, cpu))
+ cpufreq_allstats_create(cpu);
+
ret = cpufreq_stats_create_table(policy, table);
out:
@@ -401,6 +616,13 @@ static int __init cpufreq_stats_init(void)
for_each_online_cpu(cpu) {
cpufreq_update_policy(cpu);
}
+
+ create_all_freq_table();
+ ret = sysfs_create_file(cpufreq_global_kobject,
+ &_attr_all_time_in_state.attr);
+ if (ret)
+ pr_warn("Error creating sysfs file for cpufreq stats\n");
+
return 0;
}
static void __exit cpufreq_stats_exit(void)
@@ -416,6 +638,7 @@ static void __exit cpufreq_stats_exit(void)
cpufreq_stats_free_table(cpu);
cpufreq_stats_free_sysfs(cpu);
}
+ cpufreq_allstats_free();
}
MODULE_AUTHOR("Zou Nan hai <nanhai.zou@intel.com>");
diff --git a/drivers/gpu/ion/ion_iommu_heap.c b/drivers/gpu/ion/ion_iommu_heap.c
index d492c84..910b3fe 100644
--- a/drivers/gpu/ion/ion_iommu_heap.c
+++ b/drivers/gpu/ion/ion_iommu_heap.c
@@ -46,8 +46,6 @@ struct ion_iommu_priv_data {
unsigned long size;
};
-#define MAX_VMAP_RETRIES 10
-
static const unsigned int orders[] = {8, 4, 0};
static const int num_orders = ARRAY_SIZE(orders);
@@ -84,6 +82,8 @@ static struct page_info *alloc_largest_available(unsigned long size,
} else {
gfp |= GFP_KERNEL;
}
+
+ gfp |= __GFP_ZERO;
page = alloc_pages(gfp, orders[i]);
if (!page)
continue;
@@ -110,8 +110,7 @@ static int ion_iommu_heap_allocate(struct ion_heap *heap,
struct scatterlist *sg;
struct sg_table *table;
int j;
- void *ptr = NULL;
- unsigned int npages_to_vmap, total_pages, num_large_pages = 0;
+ unsigned int num_large_pages = 0;
long size_remaining = PAGE_ALIGN(size);
unsigned int max_order = orders[0];
@@ -166,40 +165,6 @@ static int ion_iommu_heap_allocate(struct ion_heap *heap,
kfree(info);
}
- /*
- * As an optimization, we omit __GFP_ZERO from
- * alloc_page above and manually zero out all of the
- * pages in one fell swoop here. To safeguard against
- * insufficient vmalloc space, we only vmap
- * `npages_to_vmap' at a time, starting with a
- * conservative estimate of 1/8 of the total number of
- * vmalloc pages available. Note that the `pages'
- * array is composed of all 4K pages, irrespective of
- * the size of the pages on the sg list.
- */
- npages_to_vmap = ((VMALLOC_END - VMALLOC_START)/8)
- >> PAGE_SHIFT;
- total_pages = data->nrpages;
- for (i = 0; i < total_pages; i += npages_to_vmap) {
- npages_to_vmap = min(npages_to_vmap, total_pages - i);
- for (j = 0; j < MAX_VMAP_RETRIES && npages_to_vmap;
- ++j) {
- ptr = vmap(&data->pages[i], npages_to_vmap,
- VM_IOREMAP, pgprot_kernel);
- if (ptr)
- break;
- else
- npages_to_vmap >>= 1;
- }
- if (!ptr) {
- pr_err("Couldn't vmap the pages for zeroing\n");
- ret = -ENOMEM;
- goto err3;
- }
- memset(ptr, 0, npages_to_vmap * PAGE_SIZE);
- vunmap(ptr);
- }
-
if (!ION_IS_CACHED(flags))
dma_sync_sg_for_device(NULL, table->sgl, table->nents,
DMA_BIDIRECTIONAL);
@@ -211,8 +176,6 @@ static int ion_iommu_heap_allocate(struct ion_heap *heap,
return -ENOMEM;
}
-
-err3:
sg_free_table(buffer->sg_table);
err2:
kfree(buffer->sg_table);
diff --git a/drivers/gpu/msm/Kconfig b/drivers/gpu/msm/Kconfig
index 96a935d..e8733cf 100644
--- a/drivers/gpu/msm/Kconfig
+++ b/drivers/gpu/msm/Kconfig
@@ -97,10 +97,3 @@ config MSM_KGSL_DISABLE_SHADOW_WRITES
default n
depends on MSM_KGSL
-config MSM_KGSL_SIMPLE_GOV
- bool "Simple KGSL GPU govenor for Qualcomm Adreno xxx devices"
- default n
- depends on MSM_KGSL
- ---help---
- A simple KGSL GPU govenor for Qualcom Adreno XXX devices
-
diff --git a/drivers/gpu/msm/Makefile b/drivers/gpu/msm/Makefile
index 9c26f44..e6ab227 100644
--- a/drivers/gpu/msm/Makefile
+++ b/drivers/gpu/msm/Makefile
@@ -25,8 +25,8 @@ msm_adreno-y += \
adreno_dispatch.o \
adreno_postmortem.o \
adreno_snapshot.o \
- adreno_trace.o \
adreno_coresight.o \
+ adreno_trace.o \
adreno_a2xx.o \
adreno_a2xx_trace.o \
adreno_a2xx_snapshot.o \
diff --git a/drivers/gpu/msm/a2xx_reg.h b/drivers/gpu/msm/a2xx_reg.h
index c70c4eb..b2fb99f 100644
--- a/drivers/gpu/msm/a2xx_reg.h
+++ b/drivers/gpu/msm/a2xx_reg.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2007-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2002,2007-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -252,7 +252,15 @@ union reg_cp_rb_cntl {
#define REG_CP_CSQ_IB1_STAT 0x01FE
#define REG_CP_CSQ_IB2_STAT 0x01FF
#define REG_CP_CSQ_RB_STAT 0x01FD
+
#define REG_CP_DEBUG 0x01FC
+/*
+ * CP DEBUG settings for a3xx and a2xx cores:
+ * DYNAMIC_CLK_DISABLE [27] - turn off the dynamic clock control
+ * MIU_128BIT_WRITE_ENABLE [25] - Allow 128 bit writes to the VBIF
+ */
+#define A2XX_CP_DEBUG_DEFAULT ((1 << 27) | (1 << 25))
+
#define REG_CP_IB1_BASE 0x0458
#define REG_CP_IB1_BUFSZ 0x0459
#define REG_CP_IB2_BASE 0x045A
diff --git a/drivers/gpu/msm/a4xx_reg.h b/drivers/gpu/msm/a4xx_reg.h
index 56147f7..53ed86d 100644
--- a/drivers/gpu/msm/a4xx_reg.h
+++ b/drivers/gpu/msm/a4xx_reg.h
@@ -24,17 +24,201 @@
#define A4XX_RBBM_AHB_CTL1 0x24
#define A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x2b
#define A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x2f
-#define A4XX_RBBM_AHB_ERROR_STATUS 0x18f
-#define A4XX_RBBM_STATUS 0x191
#define A4XX_RBBM_INT_CLEAR_CMD 0x36
#define A4XX_RBBM_INT_0_MASK 0x37
-#define A4XX_RBBM_INT_0_STATUS 0x17d
-#define A4XX_RBBM_PERFCTR_CTL 0x170
-#define A4XX_RBBM_PERFCTR_LOAD_CMD0 0x171
-#define A4XX_RBBM_PERFCTR_LOAD_CMD1 0x172
-#define A4XX_RBBM_PERFCTR_LOAD_CMD2 0x173
-#define A4XX_RBBM_GPU_BUSY_MASKED 0x17a
-#define A4XX_RBBM_PERFCTR_PWR_1_LO 0x168
+
+#define A4XX_RBBM_PERFCTR_CP_0_LO 0x9c
+#define A4XX_RBBM_PERFCTR_CP_0_HI 0x9d
+#define A4XX_RBBM_PERFCTR_CP_1_LO 0x9e
+#define A4XX_RBBM_PERFCTR_CP_1_HI 0x9f
+#define A4XX_RBBM_PERFCTR_RBBM_0_LO 0xac
+#define A4XX_RBBM_PERFCTR_RBBM_0_HI 0xad
+#define A4XX_RBBM_PERFCTR_RBBM_1_LO 0xae
+#define A4XX_RBBM_PERFCTR_RBBM_1_HI 0xaf
+#define A4XX_RBBM_PERFCTR_RBBM_2_LO 0xb0
+#define A4XX_RBBM_PERFCTR_RBBM_2_HI 0xb1
+#define A4XX_RBBM_PERFCTR_RBBM_3_LO 0xb2
+#define A4XX_RBBM_PERFCTR_RBBM_3_HI 0xb3
+#define A4XX_RBBM_PERFCTR_PC_0_LO 0xb4
+#define A4XX_RBBM_PERFCTR_PC_0_HI 0xb5
+#define A4XX_RBBM_PERFCTR_PC_1_LO 0xb6
+#define A4XX_RBBM_PERFCTR_PC_1_HI 0xb7
+#define A4XX_RBBM_PERFCTR_PC_2_LO 0xb8
+#define A4XX_RBBM_PERFCTR_PC_2_HI 0xb9
+#define A4XX_RBBM_PERFCTR_PC_3_LO 0xba
+#define A4XX_RBBM_PERFCTR_PC_3_HI 0xbb
+#define A4XX_RBBM_PERFCTR_PC_4_LO 0xbc
+#define A4XX_RBBM_PERFCTR_PC_4_HI 0xbd
+#define A4XX_RBBM_PERFCTR_PC_5_LO 0xbe
+#define A4XX_RBBM_PERFCTR_PC_5_HI 0xbf
+#define A4XX_RBBM_PERFCTR_PC_6_LO 0xc0
+#define A4XX_RBBM_PERFCTR_PC_6_HI 0xc1
+#define A4XX_RBBM_PERFCTR_PC_7_LO 0xc2
+#define A4XX_RBBM_PERFCTR_PC_7_HI 0xc3
+#define A4XX_RBBM_PERFCTR_VFD_0_LO 0xc4
+#define A4XX_RBBM_PERFCTR_VFD_0_HI 0xc5
+#define A4XX_RBBM_PERFCTR_VFD_1_LO 0xc6
+#define A4XX_RBBM_PERFCTR_VFD_1_HI 0xc7
+#define A4XX_RBBM_PERFCTR_VFD_2_LO 0xc8
+#define A4XX_RBBM_PERFCTR_VFD_2_HI 0xc9
+#define A4XX_RBBM_PERFCTR_VFD_3_LO 0xca
+#define A4XX_RBBM_PERFCTR_VFD_3_HI 0xcb
+#define A4XX_RBBM_PERFCTR_VFD_4_LO 0xcc
+#define A4XX_RBBM_PERFCTR_VFD_4_HI 0xcd
+#define A4XX_RBBM_PERFCTR_VFD_5_LO 0xce
+#define A4XX_RBBM_PERFCTR_VFD_5_HI 0xcf
+#define A4XX_RBBM_PERFCTR_VFD_6_LO 0xd0
+#define A4XX_RBBM_PERFCTR_VFD_6_HI 0xd1
+#define A4XX_RBBM_PERFCTR_VFD_7_LO 0xd2
+#define A4XX_RBBM_PERFCTR_VFD_7_HI 0xd3
+#define A4XX_RBBM_PERFCTR_HLSQ_0_LO 0xd4
+#define A4XX_RBBM_PERFCTR_HLSQ_0_HI 0xd5
+#define A4XX_RBBM_PERFCTR_HLSQ_1_LO 0xd6
+#define A4XX_RBBM_PERFCTR_HLSQ_1_HI 0xd7
+#define A4XX_RBBM_PERFCTR_HLSQ_2_LO 0xd8
+#define A4XX_RBBM_PERFCTR_HLSQ_2_HI 0xd9
+#define A4XX_RBBM_PERFCTR_HLSQ_3_LO 0xda
+#define A4XX_RBBM_PERFCTR_HLSQ_3_HI 0xdb
+#define A4XX_RBBM_PERFCTR_HLSQ_4_LO 0xdc
+#define A4XX_RBBM_PERFCTR_HLSQ_4_HI 0xdd
+#define A4XX_RBBM_PERFCTR_HLSQ_5_LO 0xde
+#define A4XX_RBBM_PERFCTR_HLSQ_5_HI 0xdf
+#define A4XX_RBBM_PERFCTR_HLSQ_6_LO 0xe0
+#define A4XX_RBBM_PERFCTR_HLSQ_6_HI 0xe1
+#define A4XX_RBBM_PERFCTR_HLSQ_7_LO 0xe2
+#define A4XX_RBBM_PERFCTR_HLSQ_7_HI 0xe3
+#define A4XX_RBBM_PERFCTR_VPC_0_LO 0xe4
+#define A4XX_RBBM_PERFCTR_VPC_0_HI 0xe5
+#define A4XX_RBBM_PERFCTR_VPC_1_LO 0xe6
+#define A4XX_RBBM_PERFCTR_VPC_1_HI 0xe7
+#define A4XX_RBBM_PERFCTR_VPC_2_LO 0xe8
+#define A4XX_RBBM_PERFCTR_VPC_2_HI 0xe9
+#define A4XX_RBBM_PERFCTR_VPC_3_LO 0xea
+#define A4XX_RBBM_PERFCTR_VPC_3_HI 0xeb
+#define A4XX_RBBM_PERFCTR_CCU_0_LO 0xec
+#define A4XX_RBBM_PERFCTR_CCU_0_HI 0xed
+#define A4XX_RBBM_PERFCTR_CCU_1_LO 0xee
+#define A4XX_RBBM_PERFCTR_CCU_1_HI 0xef
+#define A4XX_RBBM_PERFCTR_CCU_2_LO 0xf0
+#define A4XX_RBBM_PERFCTR_CCU_2_HI 0xf1
+#define A4XX_RBBM_PERFCTR_CCU_3_LO 0xf2
+#define A4XX_RBBM_PERFCTR_CCU_3_HI 0xf3
+#define A4XX_RBBM_PERFCTR_TSE_0_LO 0xf4
+#define A4XX_RBBM_PERFCTR_TSE_0_HI 0xf5
+#define A4XX_RBBM_PERFCTR_TSE_1_LO 0xf6
+#define A4XX_RBBM_PERFCTR_TSE_1_HI 0xf7
+#define A4XX_RBBM_PERFCTR_TSE_2_LO 0xf8
+#define A4XX_RBBM_PERFCTR_TSE_2_HI 0xf9
+#define A4XX_RBBM_PERFCTR_TSE_3_LO 0xfa
+#define A4XX_RBBM_PERFCTR_TSE_3_HI 0xfb
+#define A4XX_RBBM_PERFCTR_RAS_0_LO 0xfc
+#define A4XX_RBBM_PERFCTR_RAS_0_HI 0xfd
+#define A4XX_RBBM_PERFCTR_RAS_1_LO 0xfe
+#define A4XX_RBBM_PERFCTR_RAS_1_HI 0xff
+#define A4XX_RBBM_PERFCTR_RAS_2_LO 0x100
+#define A4XX_RBBM_PERFCTR_RAS_2_HI 0x101
+#define A4XX_RBBM_PERFCTR_RAS_3_LO 0x102
+#define A4XX_RBBM_PERFCTR_RAS_3_HI 0x103
+#define A4XX_RBBM_PERFCTR_UCHE_0_LO 0x104
+#define A4XX_RBBM_PERFCTR_UCHE_0_HI 0x105
+#define A4XX_RBBM_PERFCTR_UCHE_1_LO 0x106
+#define A4XX_RBBM_PERFCTR_UCHE_1_HI 0x107
+#define A4XX_RBBM_PERFCTR_UCHE_2_LO 0x108
+#define A4XX_RBBM_PERFCTR_UCHE_2_HI 0x109
+#define A4XX_RBBM_PERFCTR_UCHE_3_LO 0x10a
+#define A4XX_RBBM_PERFCTR_UCHE_3_HI 0x10b
+#define A4XX_RBBM_PERFCTR_UCHE_4_LO 0x10c
+#define A4XX_RBBM_PERFCTR_UCHE_4_HI 0x10d
+#define A4XX_RBBM_PERFCTR_UCHE_5_LO 0x10e
+#define A4XX_RBBM_PERFCTR_UCHE_5_HI 0x10f
+#define A4XX_RBBM_PERFCTR_UCHE_6_LO 0x110
+#define A4XX_RBBM_PERFCTR_UCHE_6_HI 0x111
+#define A4XX_RBBM_PERFCTR_UCHE_7_LO 0x112
+#define A4XX_RBBM_PERFCTR_UCHE_7_HI 0x113
+#define A4XX_RBBM_PERFCTR_TP_0_LO 0x114
+#define A4XX_RBBM_PERFCTR_TP_0_HI 0x115
+#define A4XX_RBBM_PERFCTR_TP_1_LO 0x116
+#define A4XX_RBBM_PERFCTR_TP_1_HI 0x117
+#define A4XX_RBBM_PERFCTR_TP_2_LO 0x118
+#define A4XX_RBBM_PERFCTR_TP_2_HI 0x119
+#define A4XX_RBBM_PERFCTR_TP_3_LO 0x11a
+#define A4XX_RBBM_PERFCTR_TP_3_HI 0x11b
+#define A4XX_RBBM_PERFCTR_TP_4_LO 0x11c
+#define A4XX_RBBM_PERFCTR_TP_4_HI 0x11d
+#define A4XX_RBBM_PERFCTR_TP_5_LO 0x11e
+#define A4XX_RBBM_PERFCTR_TP_5_HI 0x11f
+#define A4XX_RBBM_PERFCTR_TP_6_LO 0x120
+#define A4XX_RBBM_PERFCTR_TP_6_HI 0x121
+#define A4XX_RBBM_PERFCTR_TP_7_LO 0x122
+#define A4XX_RBBM_PERFCTR_TP_7_HI 0x123
+#define A4XX_RBBM_PERFCTR_SP_0_LO 0x124
+#define A4XX_RBBM_PERFCTR_SP_0_HI 0x125
+#define A4XX_RBBM_PERFCTR_SP_1_LO 0x126
+#define A4XX_RBBM_PERFCTR_SP_1_HI 0x127
+#define A4XX_RBBM_PERFCTR_SP_2_LO 0x128
+#define A4XX_RBBM_PERFCTR_SP_2_HI 0x129
+#define A4XX_RBBM_PERFCTR_SP_3_LO 0x12a
+#define A4XX_RBBM_PERFCTR_SP_3_HI 0x12b
+#define A4XX_RBBM_PERFCTR_SP_4_LO 0x12c
+#define A4XX_RBBM_PERFCTR_SP_4_HI 0x12d
+#define A4XX_RBBM_PERFCTR_SP_5_LO 0x12e
+#define A4XX_RBBM_PERFCTR_SP_5_HI 0x12f
+#define A4XX_RBBM_PERFCTR_SP_6_LO 0x130
+#define A4XX_RBBM_PERFCTR_SP_6_HI 0x131
+#define A4XX_RBBM_PERFCTR_SP_7_LO 0x132
+#define A4XX_RBBM_PERFCTR_SP_7_HI 0x133
+#define A4XX_RBBM_PERFCTR_SP_8_LO 0x134
+#define A4XX_RBBM_PERFCTR_SP_8_HI 0x135
+#define A4XX_RBBM_PERFCTR_SP_9_LO 0x136
+#define A4XX_RBBM_PERFCTR_SP_9_HI 0x137
+#define A4XX_RBBM_PERFCTR_SP_10_LO 0x138
+#define A4XX_RBBM_PERFCTR_SP_10_HI 0x139
+#define A4XX_RBBM_PERFCTR_SP_11_LO 0x13a
+#define A4XX_RBBM_PERFCTR_SP_11_HI 0x13b
+#define A4XX_RBBM_PERFCTR_RB_0_LO 0x13c
+#define A4XX_RBBM_PERFCTR_RB_0_HI 0x13d
+#define A4XX_RBBM_PERFCTR_RB_1_LO 0x13e
+#define A4XX_RBBM_PERFCTR_RB_1_HI 0x13f
+#define A4XX_RBBM_PERFCTR_RB_2_LO 0x140
+#define A4XX_RBBM_PERFCTR_RB_2_HI 0x141
+#define A4XX_RBBM_PERFCTR_RB_3_LO 0x142
+#define A4XX_RBBM_PERFCTR_RB_3_HI 0x143
+#define A4XX_RBBM_PERFCTR_RB_4_LO 0x144
+#define A4XX_RBBM_PERFCTR_RB_4_HI 0x145
+#define A4XX_RBBM_PERFCTR_RB_5_LO 0x146
+#define A4XX_RBBM_PERFCTR_RB_5_HI 0x147
+#define A4XX_RBBM_PERFCTR_RB_6_LO 0x148
+#define A4XX_RBBM_PERFCTR_RB_6_HI 0x149
+#define A4XX_RBBM_PERFCTR_RB_7_LO 0x14a
+#define A4XX_RBBM_PERFCTR_RB_7_HI 0x14b
+#define A4XX_RBBM_PERFCTR_VSC_0_LO 0x14c
+#define A4XX_RBBM_PERFCTR_VSC_0_HI 0x14d
+#define A4XX_RBBM_PERFCTR_VSC_1_LO 0x14e
+#define A4XX_RBBM_PERFCTR_VSC_1_HI 0x14f
+#define A4XX_RBBM_PERFCTR_PWR_0_LO 0x166
+#define A4XX_RBBM_PERFCTR_PWR_0_HI 0x167
+#define A4XX_RBBM_PERFCTR_PWR_1_LO 0x168
+#define A4XX_RBBM_PERFCTR_PWR_1_HI 0x169
+#define A4XX_RBBM_PERFCTR_CTL 0x170
+#define A4XX_RBBM_PERFCTR_LOAD_CMD0 0x171
+#define A4XX_RBBM_PERFCTR_LOAD_CMD1 0x172
+#define A4XX_RBBM_PERFCTR_LOAD_CMD2 0x173
+#define A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x176
+#define A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x177
+#define A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x178
+#define A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x179
+#define A4XX_RBBM_GPU_BUSY_MASKED 0x17a
+#define A4XX_RBBM_INT_0_STATUS 0x17d
+#define A4XX_RBBM_AHB_ERROR_STATUS 0x18f
+#define A4XX_RBBM_STATUS 0x191
+#define A4XX_RBBM_CFG_COUNTER0 0x1a2
+#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF0 0x1a9
+#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF1 0x1aa
+#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF2 0x1ab
+#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF3 0x1ac
+#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4 0x1ad
+#define A4XX_RBBM_CFG_DEBBUS_MISR0 0x1ae
+#define A4XX_RBBM_CFG_DEBBUS_MISR1 0x1af
/* CP registers */
#define A4XX_CP_SCRATCH_REG0 0x578
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 9c9b761..ece632c 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -17,9 +17,9 @@
#include <linux/sched.h>
#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/msm_kgsl.h>
#include <linux/delay.h>
#include <linux/of_coresight.h>
+#include <linux/input.h>
#include <mach/socinfo.h>
#include <mach/msm_bus_board.h>
@@ -78,6 +78,9 @@
#define KGSL_LOG_LEVEL_DEFAULT 3
+static void adreno_start_work(struct work_struct *work);
+static void adreno_input_work(struct work_struct *work);
+
static const struct kgsl_functable adreno_functable;
static struct adreno_device device_3d0 = {
@@ -124,10 +127,16 @@ static struct adreno_device device_3d0 = {
.ft_pf_policy = KGSL_FT_PAGEFAULT_DEFAULT_POLICY,
.fast_hang_detect = 1,
.long_ib_detect = 1,
+ .start_work = __WORK_INITIALIZER(device_3d0.start_work,
+ adreno_start_work),
+ .input_work = __WORK_INITIALIZER(device_3d0.input_work,
+ adreno_input_work),
};
unsigned int ft_detect_regs[FT_DETECT_REGS_COUNT];
+static struct workqueue_struct *adreno_wq;
+
/*
* This is the master list of all GPU cores that are supported by this
* driver.
@@ -162,6 +171,12 @@ static const struct {
unsigned int pfp_jt_idx;
/* PFP jump table load addr */
unsigned int pfp_jt_addr;
+ /* PM4 bootstrap loader size */
+ unsigned int pm4_bstrp_size;
+ /* PFP bootstrap loader size */
+ unsigned int pfp_bstrp_size;
+ /* PFP bootstrap loader supported version */
+ unsigned int pfp_bstrp_ver;
} adreno_gpulist[] = {
{ ADRENO_REV_A200, 0, 2, ANY_ID, ANY_ID,
@@ -199,7 +214,8 @@ static const struct {
512, 0, 2, SZ_512K, 0x3FF037, 0x3FF016 },
{ ADRENO_REV_A330, 3, 3, 0, ANY_ID,
"a330_pm4.fw", "a330_pfp.fw", &adreno_a3xx_gpudev,
- 512, 0, 2, SZ_1M, NO_VER, NO_VER, 0x8AD, 0x2E4, 0x201, 0x200 },
+ 512, 0, 2, SZ_1M, NO_VER, NO_VER, 0x8AD, 0x2E4, 0x201, 0x200,
+ 0x6, 0x20, 0x330020 },
{ ADRENO_REV_A305B, 3, 0, 5, 0x10,
"a330_pm4.fw", "a330_pfp.fw", &adreno_a3xx_gpudev,
512, 0, 2, SZ_128K, NO_VER, NO_VER, 0x8AD, 0x2E4,
@@ -217,6 +233,124 @@ static const struct {
512, 0, 2, (SZ_1M + SZ_512K), NO_VER, NO_VER },
};
+/* Nice level for the higher priority GPU start thread */
+static int _wake_nice = -7;
+
+/* Number of milliseconds to stay active active after a wake on touch */
+static unsigned int _wake_timeout = 100;
+
+/*
+ * A workqueue callback responsible for actually turning on the GPU after a
+ * touch event. kgsl_pwrctrl_wake() is used without any active_count protection
+ * to avoid the need to maintain state. Either somebody will start using the
+ * GPU or the idle timer will fire and put the GPU back into slumber
+ */
+static void adreno_input_work(struct work_struct *work)
+{
+ struct adreno_device *adreno_dev = container_of(work,
+ struct adreno_device, input_work);
+ struct kgsl_device *device = &adreno_dev->dev;
+
+ if (!_wake_timeout)
+ return;
+
+ mutex_lock(&device->mutex);
+
+ device->flags |= KGSL_FLAG_WAKE_ON_TOUCH;
+
+ /*
+ * Schedule adreno_start in a high priority workqueue.
+ */
+ kgsl_pwrctrl_wake(device, 1);
+
+ /*
+ * When waking up from a touch event we want to stay active long enough
+ * for the user to send a draw command. The default idle timer timeout
+ * is shorter than we want so go ahead and push the idle timer out
+ * further for this special case
+ */
+ mod_timer(&device->idle_timer,
+ jiffies + msecs_to_jiffies(_wake_timeout));
+ mutex_unlock(&device->mutex);
+}
+
+/*
+ * Process input events and schedule work if needed. At this point we are only
+ * interested in groking EV_ABS touchscreen events
+ */
+static void adreno_input_event(struct input_handle *handle, unsigned int type,
+ unsigned int code, int value)
+{
+ struct kgsl_device *device = handle->handler->private;
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+