RISC-V Single and Double Precision Floating Point extension

CMakeLists.txt

@@ -124,7 +124,7 @@ FetchContent_MakeAvailable_Args(yaml-cpp EXCLUDE_FROM_ALL)
 option(SIMENG_ENABLE_TESTS "Whether to enable testing for SimEng" OFF)
 option(SIMENG_USE_EXTERNAL_LLVM "Use an external LLVM rather than building it as a submodule" OFF)
 option(SIMENG_SANITIZE "Enable compiler sanitizers" OFF)
-option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizatoins" OFF)
+option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizations" OFF)
 option(SIMENG_ENABLE_SST "Compile SimEng SST Wrapper" OFF)
 option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF)
 
@@ -203,7 +203,7 @@ if(SIMENG_ENABLE_TESTS)
                  PATHS "${llvm_BINARY_DIR}/lib/cmake/llvm")
 
     # NOTE: we don't do the usual version checks here because it needs vars exported in find_LLVM
-    # we just assume it's good beacuse it must be whitelisted in FetchContent_Declare
+    # we just assume it's good because it must be whitelisted in FetchContent_Declare
 endif()
 
   set(SIMENG_LLVM_VERSION ${LLVM_VERSION_MAJOR} CACHE INTERNAL "LLVM major version number used.")

configs/DEMO_RISCV.yaml

@@ -7,11 +7,12 @@ Core:
   ISA: rv64
   Simulation-Mode: outoforder
   Clock-Frequency: 2.5
-  Fetch-Block-Size: 32
+  # Timer-Frequency is in MHz.
+  Timer-Frequency: 200
 Fetch:
   Fetch-Block-Size: 32
-  Loop-Buffer-Size: 0
-  Loop-Detection-Threshold: 0
+  Loop-Buffer-Size: 64
+  Loop-Detection-Threshold: 4
 Process-Image:
   Heap-Size: 1073741824
   Stack-Size: 1048576
@@ -20,7 +21,6 @@ Register-Set:
   FloatingPoint-Count: 90
 Pipeline-Widths:
   Commit: 4
-  Dispatch-Rate: 4
   FrontEnd: 4
   LSQ-Completion: 2
 Queue-Sizes:
@@ -31,10 +31,8 @@ Branch-Predictor:
   BTB-Tag-Bits: 11
   Saturating-Count-Bits: 2
   Global-History-Length: 10
-  RAS-entries: 1
+  RAS-entries: 5
   Fallback-Static-Predictor: "Always-Taken"
-  Branch-Predictor:
-  BTB-bitlength: 16
 L1-Data-Memory:
   Interface-Type: Fixed
 L1-Instruction-Memory:
@@ -53,10 +51,12 @@ Ports:
     Instruction-Support:
       - INT_SIMPLE
       - INT_MUL
+      - FLOAT
   1:
     Portname: Port 1
     Instruction-Support:
       - INT
+      - FLOAT
   2:
     Portname: Port 2
     Instruction-Support:
@@ -113,9 +113,29 @@ Latencies:
     Execution-Throughput: 1
   2:
     Instruction-Groups:
-      - INT_DIV
+      - INT_DIV_OR_SQRT
     Execution-Latency: 39
     Execution-Throughput: 39
+  3:
+    Instruction-Groups:
+      - FLOAT_SIMPLE_CMP
+    Execution-Latency: 5
+    Execution-Throughput: 1
+  4:
+    Instruction-Groups:
+      - FLOAT_MUL
+    Execution-Latency: 6
+    Execution-Throughput: 1
+  5:
+    Instruction-Groups:
+      - FLOAT_SIMPLE_CVT
+    Execution-Latency: 7
+    Execution-Throughput: 1
+  6:
+    Instruction-Groups:
+      - FLOAT_DIV_OR_SQRT
+    Execution-Latency: 16
+    Execution-Throughput: 16
 # CPU-Info mainly used to generate a replica of the special (or system) file directory
 # structure
 CPU-Info:
@@ -126,7 +146,7 @@ CPU-Info:
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)
   Socket-Count: 1
-  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (TX2 true value is 4)
+  # SMT MUST be 1 as Simultaneous-Multi-Threading is not supported at this time. (TX2 true value is 4)
   SMT: 1
   # Below are the values needed to generate /proc/cpuinfo
   BogoMIPS: 400.00

configs/sst-cores/a64fx-sst.yaml

@@ -255,7 +255,7 @@ CPU-Info:
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)
   Socket-Count: 1
-  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (A64FX true value is 1)
+  # SMT MUST be 1 as Simultaneous-Multi-Threading is not supported at this time. (A64FX true value is 1)
   SMT: 1
   # Below are the values needed to generate /proc/cpuinfo
   BogoMIPS: 200.00

docs/sphinx/developer/arch/supported/aarch64.rst

@@ -158,7 +158,7 @@ Also supported is the Arm SME extension and thus the use of ``ZA`` sub-tile regi
 
 SME instructions can also operate on sub-tile slices; individual rows or columns within a sub-tile. Regardless of whether a whole sub-tile or a slice is used as a source operand, all rows associated with said tile will be added to the ``operands`` vector. There are two reasons for this. First, the index value pointing to the relevant slice cannot be evaluated before instruction execution, thus, all sub-tile rows need to be provided. Second, if the source slice is a vertical slice (or a column of the sub-tile) then an element from each row is needed to construct the correct output.
 
-Furthermore, a similar situation is present when a sub-tile slice is a destination operand. The ``results`` vector will expect a ``registerValue`` entry for each row of the targetted sub-tile, again due to the same two reasons listed previously. But, when a sub-tile slice is a destination operand, **all** associated rows of the sub-tile will also be added to the ``operands`` vector. Again, this is down to two key, similar reasons. First, when a destination is a sub-tile slice, we only want to update that row or column. As the we are unable to calculate which slice will be our destination before execution has commenced, all possible slices must be added to the ``results`` vector. If we were to not provide a ``RegisterValue`` to each entry of the ``results`` vector, the default value is 0. Therefore, in order to not zero-out the other slices within the sub-tile we will need access to their current values. Secondly, if the destination is a vertical slice (or sub-tile column) then only one element per row should be updated; the rest should remain unchanged.
+Furthermore, a similar situation is present when a sub-tile slice is a destination operand. The ``results`` vector will expect a ``registerValue`` entry for each row of the targeted sub-tile, again due to the same two reasons listed previously. But, when a sub-tile slice is a destination operand, **all** associated rows of the sub-tile will also be added to the ``operands`` vector. Again, this is down to two key, similar reasons. First, when a destination is a sub-tile slice, we only want to update that row or column. As the we are unable to calculate which slice will be our destination before execution has commenced, all possible slices must be added to the ``results`` vector. If we were to not provide a ``RegisterValue`` to each entry of the ``results`` vector, the default value is 0. Therefore, in order to not zero-out the other slices within the sub-tile we will need access to their current values. Secondly, if the destination is a vertical slice (or sub-tile column) then only one element per row should be updated; the rest should remain unchanged.
 
 Before implementing any further SME functionality we highly recommend familiarising yourself with the specification; found `here <https://developer.arm.com/documentation/ddi0616/latest>`_.
 

docs/sphinx/developer/arch/supported/riscv.rst

@@ -1,7 +1,7 @@
 RISCV
 =======
 
-SimEng provides an almost complete implementation of the rv64ima architecture, as well as being capable of handling some supervisor call (syscall) exceptions via basic system call emulation. This is sufficient to run many simple single threaded programs that have been statically compiled with the standard library.
+SimEng provides an almost complete implementation of the rv64imafd architecture, as well as being capable of handling some supervisor call (syscall) exceptions via basic system call emulation. This is sufficient to run many simple single threaded programs that have been statically compiled with the standard library.
 
 .. contents:: Contents
 
@@ -21,6 +21,8 @@ The logic held in ``src/lib/arch/riscv/Instruction_decode.cc`` is primarily asso
 - ``isAtomic_``, is an atomic operation.
 - ``isLogical_``, is a logical operation e.g bitwise and.
 - ``isCompare_``, is a compare operation.
+- ``isFloat_``, is a floating point operation.
+- ``isConvert_``, is a floating point to integer conversion operation.
 
 .. _riscv-instruction-groups:
 
@@ -35,6 +37,9 @@ The above diagram follows the same structure as :ref:`AArch64 instruction groups
 
 This hierarchy-based naming convention has been chosen to provide the user with greater control over the number of instructions grouped under one name, whilst also remaining intuitive. A variety of combinations/instruction scopes can be defined through this method and only uses a small set of easily interpreted operation descriptions.
 
+        .. Note::
+                INT_SIMPLE_CVT and FLOAT_SIMPLE_SHIFT are both invalid instruction groups
+
 If the supplied instruction groups don't provide a small enough scope, a Capstone opcode can be used instead (found in ``SimEng/build/_deps/capstone-lib-src/arch/RISCV/RISCVGenInstrInfo.inc``) with the format ``~{CAPSTONE_OPCODE}``.
 
 .. _riscv-adding-instructions:
@@ -78,3 +83,17 @@ An example of this would be the pseudoinstruction ``not rd, rs``. This is implem
 This must be fixed in the ``InstructionMetadata`` constructor. A new entry should be added to the switch statement and the pseudoinstruction mnemonic checked. The correct set of operands can then be set. A couple of helper functions are used for common operand fixes.
 
 To ensure all pseudoinstructions are accounted for, the table in chapter 25 of the `RISC-V Unprivileged specification <https://riscv.org/technical/specifications/>`_ should be checked. It is recommended to implement all pseudoinstructions for all currently implemented instructions.
+
+Rounding Modes
+**************
+
+RISC-V floating point instructions can use either static or dynamic rounding modes. The former embedded as 3 bits within the instruction encoding, and the later held as 3 bits of the ``fcsr`` system register.
+
+To enforce static rounding modes, the function ``setStaticRoundingModeThen`` is used. This takes the execution logic of the instruction as a parameter in the form of a lambda function. ``setStaticRoundingModeThen`` extracts the rounding mode from the raw instruction encoding as Capstone currently doesn't perform this functionality. It then changes the C++ ``fenv`` rounding mode before calling the lambda to perform the execution logic within this new environment. Before returning execution to the switch statement, it reverts the ``fenv`` rounding mode to its initial state to preserve the dynamic rounding mode.
+
+Updating the dynamic rounding mode can only be performed by a change to the ``fcsr`` system register. This is done using a Zicsr instruction and must happen atomically. To enforce this functionality, the relevant instruction causes a non-fatal exception. This forces all instructions earlier in program order to be committed and all instructions later to be flushed from the pipeline. This allows the ``fenv`` rounding mode to be changed while the pipeline is sterile, thus preventing incorrect rounding of speculatively executed instructions.
+
+Zicsr
+*****
+
+The Zicsr extension is required by the F and D extensions; however, this is left with dummy implementations for this release (0.9.6). Therefore, the ``fcsr`` register is not updated based on the result of operations or the changing of the rounding mode. Thus far, this has not affected our ability to run typical high performance computing applications and miniapps.

src/include/simeng/CoreInstance.hh

@@ -75,6 +75,8 @@ class CoreInstance {
   /** Getter for the set simulation mode in a string format. */
   const std::string getSimulationModeString() const;
 
+  const std::string getISAString() const;
+
   /** Getter for the create core object. */
   std::shared_ptr<simeng::Core> getCore() const;
 
@@ -169,6 +171,8 @@ class CoreInstance {
    */
   std::string modeString_ = "Emulation";
 
+  std::string instructionSetArchString_ = "";
+
   /** Reference to the SimEng data memory object. */
   std::shared_ptr<simeng::MemoryInterface> dataMemory_ = nullptr;
 

src/include/simeng/FixedLatencyMemoryInterface.hh

@@ -57,7 +57,7 @@ class FixedLatencyMemoryInterface : public MemoryInterface {
   /** Clear the completed reads. */
   void clearCompletedReads() override;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   bool hasPendingRequests() const override;
 
   /** Tick the memory model to process the request queue. */

src/include/simeng/FlatMemoryInterface.hh

@@ -27,7 +27,7 @@ class FlatMemoryInterface : public MemoryInterface {
   /** Clear the completed reads. */
   void clearCompletedReads() override;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   bool hasPendingRequests() const override;
 
   /** Tick: do nothing */

src/include/simeng/Instruction.hh

@@ -24,7 +24,7 @@ class Instruction {
   bool exceptionEncountered() const;
 
   /** Retrieve the source registers this instruction reads. */
-  virtual const span<Register> getOperandRegisters() const = 0;
+  virtual const span<Register> getSourceRegisters() const = 0;
 
   /** Retrieve the data contained in the source registers this instruction
    * reads.*/

src/include/simeng/MemoryInterface.hh

@@ -63,7 +63,7 @@ class MemoryInterface {
   /** Clear the completed reads. */
   virtual void clearCompletedReads() = 0;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   virtual bool hasPendingRequests() const = 0;
 
   /** Tick the memory interface to allow it to process internal tasks.

src/include/simeng/RegisterValue.hh

@@ -90,7 +90,7 @@ class RegisterValue {
    * the specified datatype. */
   template <class T>
   const T* getAsVector() const {
-    static_assert(alignof(T) <= 8 && "Alignment over 8 bytes not guranteed");
+    static_assert(alignof(T) <= 8 && "Alignment over 8 bytes not guaranteed");
     assert(bytes > 0 && "Attempted to access an uninitialised RegisterValue");
     assert(sizeof(T) <= bytes &&
            "Attempted to access a RegisterValue as a datatype larger than the "

src/include/simeng/arch/aarch64/Instruction.hh

@@ -224,6 +224,7 @@ enum class InstructionException {
   EncodingUnallocated,
   EncodingNotYetImplemented,
   ExecutionNotYetImplemented,
+  AliasNotYetImplemented,
   MisalignedPC,
   DataAbort,
   SupervisorCall,
@@ -277,7 +278,7 @@ class Instruction : public simeng::Instruction {
   virtual InstructionException getException() const;
 
   /** Retrieve the source registers this instruction reads. */
-  const span<Register> getOperandRegisters() const override;
+  const span<Register> getSourceRegisters() const override;
 
   /** Retrieve the data contained in the source registers this instruction
    * reads.*/

src/include/simeng/arch/aarch64/MicroDecoder.hh

@@ -20,7 +20,7 @@ struct OpType {
  */
 class MicroDecoder {
  public:
-  /** Construct a micro decoder for splitting relevant instructons. */
+  /** Construct a micro decoder for splitting relevant instructions. */
   MicroDecoder(YAML::Node config);
   ~MicroDecoder();
 
@@ -73,7 +73,7 @@ class MicroDecoder {
 
   /** A micro-decoding cache, mapping an instruction word to a previously split
    * instruction. Instructions are added to the cache as they're split into
-   * their repsective micro-operations, to reduce the overhead of future
+   * their respective micro-operations, to reduce the overhead of future
    * splitting. */
   static std::unordered_map<uint32_t, std::vector<Instruction>>
       microDecodeCache;

src/include/simeng/arch/aarch64/helpers/float.hh

@@ -138,7 +138,7 @@ class floatHelp {
    * D represents the destination vector register type (e.g. for dd, D =
    * double).
    * N represents the source vector register type (e.g. for wn, N = int32_t).
-   * Returns correctly formated RegisterValue. */
+   * Returns correctly formatted RegisterValue. */
   template <typename D, typename N>
   static RegisterValue scvtf_FixedPoint(
       std::vector<RegisterValue>& operands,

src/include/simeng/arch/riscv/Architecture.hh

@@ -14,6 +14,19 @@ namespace simeng {
 namespace arch {
 namespace riscv {
 
+// A temporary enum to hold system register addresses
+// TODO this should be removed upon relevant capstone updates
+typedef enum riscv_sysreg {
+  RISCV_SYSREG_FFLAGS = 0x001,
+  RISCV_SYSREG_FRM = 0x002,
+  RISCV_SYSREG_FCSR = 0x003,
+
+  RISCV_SYSREG_CYCLE = 0xC00,
+  RISCV_SYSREG_TIME = 0xC01,
+  RISCV_SYSREG_INSTRET = 0xC02,
+
+} riscv_sysreg;
+
 /* A basic RISC-V implementation of the `Architecture` interface. */
 class Architecture : public arch::Architecture {
  public:
@@ -95,6 +108,9 @@ class Architecture : public arch::Architecture {
 
   /** A reference to a Linux kernel object to forward syscalls to. */
   kernel::Linux& linux_;
+
+  /** System Register of Processor Cycle Counter. */
+  simeng::Register cycleSystemReg_;
 };
 
 }  // namespace riscv