-
Notifications
You must be signed in to change notification settings - Fork 0
/
lpm_bustri1_syn.v
287 lines (268 loc) · 8.61 KB
/
lpm_bustri1_syn.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition"
// DATE "04/07/2011 18:25:35"
//
// Device: Altera EP2C5T144C6 Package TQFP144
//
//
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
//
module lpm_bustri1 (
data,
enabledt,
tridata)/* synthesis synthesis_greybox=0 */;
input [7:0] data;
input enabledt;
inout [7:0] tridata;
wire gnd;
wire vcc;
assign gnd = 1'b0;
assign vcc = 1'b1;
cycloneii_io \tridata[0]~I (
.datain(data[0]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[0]));
defparam \tridata[0]~I .input_async_reset = "none";
defparam \tridata[0]~I .input_power_up = "low";
defparam \tridata[0]~I .input_register_mode = "none";
defparam \tridata[0]~I .input_sync_reset = "none";
defparam \tridata[0]~I .oe_async_reset = "none";
defparam \tridata[0]~I .oe_power_up = "low";
defparam \tridata[0]~I .oe_register_mode = "none";
defparam \tridata[0]~I .oe_sync_reset = "none";
defparam \tridata[0]~I .operation_mode = "bidir";
defparam \tridata[0]~I .output_async_reset = "none";
defparam \tridata[0]~I .output_power_up = "low";
defparam \tridata[0]~I .output_register_mode = "none";
defparam \tridata[0]~I .output_sync_reset = "none";
cycloneii_io \tridata[1]~I (
.datain(data[1]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[1]));
defparam \tridata[1]~I .input_async_reset = "none";
defparam \tridata[1]~I .input_power_up = "low";
defparam \tridata[1]~I .input_register_mode = "none";
defparam \tridata[1]~I .input_sync_reset = "none";
defparam \tridata[1]~I .oe_async_reset = "none";
defparam \tridata[1]~I .oe_power_up = "low";
defparam \tridata[1]~I .oe_register_mode = "none";
defparam \tridata[1]~I .oe_sync_reset = "none";
defparam \tridata[1]~I .operation_mode = "bidir";
defparam \tridata[1]~I .output_async_reset = "none";
defparam \tridata[1]~I .output_power_up = "low";
defparam \tridata[1]~I .output_register_mode = "none";
defparam \tridata[1]~I .output_sync_reset = "none";
cycloneii_io \tridata[2]~I (
.datain(data[2]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[2]));
defparam \tridata[2]~I .input_async_reset = "none";
defparam \tridata[2]~I .input_power_up = "low";
defparam \tridata[2]~I .input_register_mode = "none";
defparam \tridata[2]~I .input_sync_reset = "none";
defparam \tridata[2]~I .oe_async_reset = "none";
defparam \tridata[2]~I .oe_power_up = "low";
defparam \tridata[2]~I .oe_register_mode = "none";
defparam \tridata[2]~I .oe_sync_reset = "none";
defparam \tridata[2]~I .operation_mode = "bidir";
defparam \tridata[2]~I .output_async_reset = "none";
defparam \tridata[2]~I .output_power_up = "low";
defparam \tridata[2]~I .output_register_mode = "none";
defparam \tridata[2]~I .output_sync_reset = "none";
cycloneii_io \tridata[3]~I (
.datain(data[3]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[3]));
defparam \tridata[3]~I .input_async_reset = "none";
defparam \tridata[3]~I .input_power_up = "low";
defparam \tridata[3]~I .input_register_mode = "none";
defparam \tridata[3]~I .input_sync_reset = "none";
defparam \tridata[3]~I .oe_async_reset = "none";
defparam \tridata[3]~I .oe_power_up = "low";
defparam \tridata[3]~I .oe_register_mode = "none";
defparam \tridata[3]~I .oe_sync_reset = "none";
defparam \tridata[3]~I .operation_mode = "bidir";
defparam \tridata[3]~I .output_async_reset = "none";
defparam \tridata[3]~I .output_power_up = "low";
defparam \tridata[3]~I .output_register_mode = "none";
defparam \tridata[3]~I .output_sync_reset = "none";
cycloneii_io \tridata[4]~I (
.datain(data[4]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[4]));
defparam \tridata[4]~I .input_async_reset = "none";
defparam \tridata[4]~I .input_power_up = "low";
defparam \tridata[4]~I .input_register_mode = "none";
defparam \tridata[4]~I .input_sync_reset = "none";
defparam \tridata[4]~I .oe_async_reset = "none";
defparam \tridata[4]~I .oe_power_up = "low";
defparam \tridata[4]~I .oe_register_mode = "none";
defparam \tridata[4]~I .oe_sync_reset = "none";
defparam \tridata[4]~I .operation_mode = "bidir";
defparam \tridata[4]~I .output_async_reset = "none";
defparam \tridata[4]~I .output_power_up = "low";
defparam \tridata[4]~I .output_register_mode = "none";
defparam \tridata[4]~I .output_sync_reset = "none";
cycloneii_io \tridata[5]~I (
.datain(data[5]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[5]));
defparam \tridata[5]~I .input_async_reset = "none";
defparam \tridata[5]~I .input_power_up = "low";
defparam \tridata[5]~I .input_register_mode = "none";
defparam \tridata[5]~I .input_sync_reset = "none";
defparam \tridata[5]~I .oe_async_reset = "none";
defparam \tridata[5]~I .oe_power_up = "low";
defparam \tridata[5]~I .oe_register_mode = "none";
defparam \tridata[5]~I .oe_sync_reset = "none";
defparam \tridata[5]~I .operation_mode = "bidir";
defparam \tridata[5]~I .output_async_reset = "none";
defparam \tridata[5]~I .output_power_up = "low";
defparam \tridata[5]~I .output_register_mode = "none";
defparam \tridata[5]~I .output_sync_reset = "none";
cycloneii_io \tridata[6]~I (
.datain(data[6]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[6]));
defparam \tridata[6]~I .input_async_reset = "none";
defparam \tridata[6]~I .input_power_up = "low";
defparam \tridata[6]~I .input_register_mode = "none";
defparam \tridata[6]~I .input_sync_reset = "none";
defparam \tridata[6]~I .oe_async_reset = "none";
defparam \tridata[6]~I .oe_power_up = "low";
defparam \tridata[6]~I .oe_register_mode = "none";
defparam \tridata[6]~I .oe_sync_reset = "none";
defparam \tridata[6]~I .operation_mode = "bidir";
defparam \tridata[6]~I .output_async_reset = "none";
defparam \tridata[6]~I .output_power_up = "low";
defparam \tridata[6]~I .output_register_mode = "none";
defparam \tridata[6]~I .output_sync_reset = "none";
cycloneii_io \tridata[7]~I (
.datain(data[7]),
.oe(enabledt),
.outclk(gnd),
.outclkena(vcc),
.inclk(gnd),
.inclkena(vcc),
.areset(gnd),
.sreset(gnd),
.differentialin(gnd),
.linkin(gnd),
.combout(),
.regout(),
.differentialout(),
.linkout(),
.padio(tridata[7]));
defparam \tridata[7]~I .input_async_reset = "none";
defparam \tridata[7]~I .input_power_up = "low";
defparam \tridata[7]~I .input_register_mode = "none";
defparam \tridata[7]~I .input_sync_reset = "none";
defparam \tridata[7]~I .oe_async_reset = "none";
defparam \tridata[7]~I .oe_power_up = "low";
defparam \tridata[7]~I .oe_register_mode = "none";
defparam \tridata[7]~I .oe_sync_reset = "none";
defparam \tridata[7]~I .operation_mode = "bidir";
defparam \tridata[7]~I .output_async_reset = "none";
defparam \tridata[7]~I .output_power_up = "low";
defparam \tridata[7]~I .output_register_mode = "none";
defparam \tridata[7]~I .output_sync_reset = "none";
endmodule