Copyright 2012-2024 / Enjoy-Digital & LiteX developers

Welcome to LiteX!

The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.

LiteX SoC builder framework quick tour/overview: Slides

Want to get started and/or looking for documentation? Make sure to visit the Wiki!

A question or want to get in touch? Join us on Discord or on our IRC channel: [#litex at irc.libera.chat].

LiteX provides all the common components required to easily create an FPGA Core/SoC:

• ✔️ Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
• ✔️ Simple cores: RAM, ROM, Timer, UART, JTAG, etc….
• ✔️ Complex cores through the ecosystem of cores: LiteDRAM, LitePCIe, LiteEth, LiteSATA, etc...
• ✔️ Various CPUs & ISAs: RISC-V, OpenRISC, LM32, Zynq, X86 (through a PCIe), etc...
• ✔️ Mixed languages support with VHDL/Verilog/(n)Migen/Spinal-HDL/etc... integration capabilities.
• ✔️ Powerful debug infrastructure through the various bridges and Litescope.
• ✔️ Direct/Fast simulation through Verilator.
• ✔️ Build backends for open-source and vendors toolchains.
• ✔️ And a lot more... :)

By combining LiteX with the ecosystem of cores, creating complex SoCs becomes a lot easier than with traditional approaches while providing better portability and flexibility: Here is for example a Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA built and integrated with LiteX, running on a cheap repurposed Acorn CLE215+ Mining Board: For more info, have a look at Linux-on-LiteX-Vexriscv project and try running Linux on your FPGA board!

LiteX's digital logic is currently described with Migen which does not prevent users to create mixed language projects:

• It's very common and easy to integrate VHDL/Verilog/SystemVerilog/nMigen/Spinal-HDL code in LiteX!
• It's also very common to do the opposite and generate the LiteX design as a verilog file and integrate it in a traditional flow.

LiteX was initially developed by Enjoy-Digital to create projects for clients (and we are still using it for that :)) and trying to take the different clients' requirements/needs consideration made, we think, the framework very flexible:

• Some users only want to use it to easily interconnect their existing VHDL/Verilog/SV cores.
• Some users are only interested to reuse the PCIe/Ethernet/SATA/etc cores as regular core and just integrate them in their traditional flow.
• Some users with a hardware background start with the above approaches and then switch later to the full Python flow since find it more efficient.
• Some users with a software background and fluent with Python start playing with FPGAs while they would probably never touch FPGA otherwise :)
• Etc...

We are well aware that everyone has a different background, so it's up to you to pick the right approach with LiteX that will be convenient for you!

To get started we encourage you to read the wiki.

You already have a FPGA board(s)? Visit LiteX-Boards to see if your board(s) is already supported!

The framework is also far from perfect and we'll be happy to have your feedback or/and contributions.

Have fun! 😉

We share this project under a permissive BSD 2-Clause License, inspired by our fantastic community and supportive clients. If LiteX benefits your research, hobby, or commercial projects, we kindly ask for your positive collaboration and respect for the effort involved.

Thank you for helping us improve LiteX and being part of our community!

Typical LiteX design flow:

                                      +---------------+
                                      |FPGA toolchains|
                                      +----^-----+----+
                                           |     |
                                        +--+-----v--+
                       +-------+        |           |
                       | Migen +-------->           |
                       +-------+        |           |        Your design
                                        |   LiteX   +---> ready to be used!
                                        |           |
              +----------------------+  |           |
              |LiteX Cores Ecosystem +-->           |
              +----------------------+  +-^-------^-+
               (Eth, SATA, DRAM, USB,     |       |
                PCIe, Video, etc...)      +       +
                                         board   target
                                         file    file

LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:

Name	Build Status	Description
LiteX-Boards		Boards support
LiteDRAM		DRAM
LiteEth		Ethernet
LitePCIe		PCIe
LiteSATA		SATA
LiteSDCard		SD card
LiteICLink		Inter-Chip communication
LiteJESD204B