{"payload":{"header_redesign_enabled":false,"results":[{"id":"224599481","archived":false,"color":"#b2b7f8","followers":44,"has_funding_file":false,"hl_name":"VenciFreeman/RISC-V","hl_trunc_description":"A simple RISC-V CPU written in Verilog.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":224599481,"name":"RISC-V","owner_id":37969638,"owner_login":"VenciFreeman","updated_at":"2024-08-17T02:58:09.013Z","has_issues":true}},"sponsorable":false,"topics":["verilog","risc-v"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":86,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AVenciFreeman%252FRISC-V%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/VenciFreeman/RISC-V/star":{"post":"I5sQs_NyZ_MVD75WMCh7OAyHDg05sl7VjLet8BGqsiGVx1GgPLbeHn_PKXoNCrbX4XM1d_DRDSizdjDWHL5-ig"},"/VenciFreeman/RISC-V/unstar":{"post":"AgzDZtZBFQzZeaSfjYUuoNAwQQDWbxXhvn8Z1UUNU3kCzrDVE0d-brkN1XzwAfJex7hVFm7swLiHICQsd7hq0Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"9Lnv1hTTUto_2_MBJU0gnr1WgxsE36sVCUVgLYrncb-AAlX8zXEhOj9KX2jf8ll5s2WSNqAAswiZ5z1Clb2jJQ"}}},"title":"Repository search results"}