BUILDING.md

Building UPduino Example Project

WORK IN PROGRESS...

Mske targets

The following make targets are shown typing make:

make targets:
    make all        - synthesize FPGA bitstream and build simulation for design
    make bin        - synthesize UPduino bitstream for design
    make prog       - program UPduino bitstream via USB
    make count      - show design resource usage counts
    make isim       - build Icarus Verilog simulation for design
    make irun       - run Icarus Verilog simulation for design
    make vsim       - build Verilator C++ simulation for design
    make vrun       - run Verilator C++ simulation for design
    make clean      - clean most files that can be rebuilt