diff --git a/src/xeda/flows/yosys/common.py b/src/xeda/flows/yosys/common.py
index 335d398..abd906d 100644
--- a/src/xeda/flows/yosys/common.py
+++ b/src/xeda/flows/yosys/common.py
@@ -191,8 +191,6 @@ def init(self):
             ss.flatten = True  # design must be flattened
         if ss.flatten:
             append_flag(ss.synth_flags, "-flatten")
-        else:
-            append_flag(ss.synth_flags, "-noflatten")
         if ss.abc_dff:
             append_flag(ss.abc_flags, "-dff")
         ss.set_attribute = hierarchical_merge(self.design.rtl.attributes, ss.set_attribute)
diff --git a/src/xeda/flows/yosys/templates/yosys_fpga_synth.tcl b/src/xeda/flows/yosys/templates/yosys_fpga_synth.tcl
index 8b6ded9..03ce376 100644
--- a/src/xeda/flows/yosys/templates/yosys_fpga_synth.tcl
+++ b/src/xeda/flows/yosys/templates/yosys_fpga_synth.tcl
@@ -15,9 +15,11 @@ yosys flatten
 
 {% if settings.pre_synth_opt %}
 yosys log -stdout "** Pre-synthesis optimization **"
-yosys opt -full -purge -sat
+yosys opt -undriven -purge -keepdc -noff
 {% endif %}
 
+yosys opt_clean -purge
+
 {% if settings.abc9 -%}
 {% if settings.flow3 -%} yosys scratchpad -copy abc9.script.flow3 abc9.script {%- endif %}
 {# decrease the target delay to account for interconnect delay #}
@@ -38,9 +40,11 @@ yosys log -stdout "[ERROR] Unknown FPGA vendor, family, or device"
 
 {% if settings.post_synth_opt %}
 yosys log -stdout "** Post-synthesis optimization **"
-yosys opt -full -purge -sat
+yosys opt -full -fine -purge -sat -undriven
 {% endif %}
 
+yosys opt_clean -purge
+
 {% if settings.splitnets %}
 yosys splitnets
 {% endif %}
diff --git a/src/xeda/flows/yosys/yosys_fpga.py b/src/xeda/flows/yosys/yosys_fpga.py
index b7be7f9..e7306f9 100644
--- a/src/xeda/flows/yosys/yosys_fpga.py
+++ b/src/xeda/flows/yosys/yosys_fpga.py
@@ -153,8 +153,23 @@ def parse_reports(self) -> bool:
                         self.results["LUT"] += ram32m
                         self.results["LUT:RAM"] = ram32m
                     self.results["FF"] = sum_all_resources(
-                        design_util, ["FDCE", "FDPE", "FDRE", "FDSE"]
+                        design_util,
+                        [
+                            "FDCE",  # D Flip-Flop with Clock Enable and Asynchronous Clear
+                            "FDPE",  # D Flip-Flop with Clock Enable and Asynchronous Preset
+                            "FDRE",  # D Flip-Flop with Clock Enable and Synchronous Reset
+                            "FDSE",  # D Flip-Flop with Clock Enable and Synchronous Set
+                        ],
                     )
+                    latches = sum_all_resources(
+                        design_util,
+                        [
+                            "LDCE",  # Transparent Data Latch with Asynchronous Clear and Gate Enable
+                            "LDPE",  # Transparent Data Latch with Asynchronous Preset and Gate Enable
+                        ],
+                    )
+                    if latches:
+                        self.results["LATCH"] = latches
                     brams: float = sum_all_resources(design_util, ["RAMB36"])
                     brams_half = sum_all_resources(design_util, ["RAMB18"])
                     brams += brams_half / 2
@@ -163,9 +178,12 @@ def parse_reports(self) -> bool:
                     dsps = sum_all_resources(design_util, ["DSP48E1", "DSP48E2", "DSP48E"])
                     if dsps:
                         self.results["DSP"] = dsps
-                    carry_chains = sum_all_resources(design_util, ["CARRY4", "CARRY2"])
+                    carry_chains = sum_all_resources(design_util, ["CARRY8", "CARRY4", "CARRY2"])
                     if carry_chains:
                         self.results["CARRY"] = carry_chains
+                    muxf78 = sum_all_resources(design_util, ["MUXF7", "MUXF8"])
+                    if carry_chains:
+                        self.results["MUXF7/F8"] = muxf78
 
         # if self.settings.fpga:
         return True