Second PLL might be missing from chipdb of HX8k and possibly HX4k

[matthiasbock]

Lattice's website states, that iCE40-HX4k and -HX8k both feature two PLLs.

• http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40

I created a Verilog project in which I use both PLLs. Synthesis with YoSys completes successfully, however placement of the second PLL fails with both arachne-pnr and nextpnr. In the nextpnr-gui I could not find a second PLL bel, therefore I suspect it might be missing from the chipdb.

Here you can find a simple project reproducing the issue:

• https://github.com/matthiasbock/ice40-second-pll-not-placed-issue

(I tried attaching a ZIP to this issue, but for some reason that didn't work.)

Building with arachne-pnr

$ make build/arachne_pnr.bin
arachne-pnr -d 8k -P ct256 -p pinout.pcf build/top.blif -o build/arachne_pnr.asc
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
  supported packages: cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif build/top.blif...
prune...
read_pcf pinout.pcf...
instantiate_io...
pack...

After packing:
IOs          3 / 206
GBs          0 / 8
  GB_IOs     0 / 8
LCs          0 / 7680
  DFF        0
  CARRY      0
  CARRY, DFF 0
  DFF PASS   0
  CARRY PASS 0
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         2 / 2

place_constraints...
fatal error: failed to place: placed 1 PLLs of 2 / 2
Makefile:69: recipe for target 'build/arachne_pnr.asc' failed
make: *** [build/arachne_pnr.asc] Error 1

Building with nextpnr

$ make build/nextpnr.bin
nextpnr-ice40 --hx8k --freq 100 --json build/top.json --pcf pinout.pcf --asc build/nextpnr.asc
Info: Importing module top
Info: Rule checker, verifying imported design
Info: Checksum: 0x51845e2c

Info: constrained 'clock_10mhz' to bel 'X16/Y0/io1'
Info: constrained 'test1' to bel 'X7/Y33/io1'
Info: constrained 'test2' to bel 'X6/Y33/io1'

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing carries..
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'pll1.uut' to X16/Y33/pll_3
ERROR: PLL 'pll2.uut' couldn't be placed anywhere, no suitable BEL found.
ERROR: Packing design failed.
0 warnings, 2 errors
Makefile:72: recipe for target 'build/nextpnr.asc' failed
make: *** [build/nextpnr.asc] Error 255

[daveshah1]

The problem is you are using two CORE variant PLLs, which conflicts with the fact that clock_10mhz is at a dedicated PLL input pin. Use one CORE and one 2-output PAD PLL, passing the pass-through second output of the latter into the reference input of the former.