wave.vcd

$version Generated by VerilatedVcd $end
$timescale 1s $end

 $scope module TOP $end
  $var wire  1 s# RxD $end
  $var wire  1 t# TxD $end
  $var wire  1 m# clk $end
  $var wire  8 o# led [7:0] $end
  $var wire  1 n# rst $end
  $var wire  8 p# seg7_seg [7:0] $end
  $var wire  8 q# seg7_seg1 [7:0] $end
  $var wire  8 r# seg7_select [7:0] $end
  $scope module top $end
   $var wire 32 y# ClkFrequency [31:0] $end
   $var wire  1 s# RxD $end
   $var wire  1 t# TxD $end
   $var wire  1 m# clk $end
   $var wire  8 o# led [7:0] $end
   $var wire  1 n# locked $end
   $var wire  1 m# oclk $end
   $var wire  1 n# rst $end
   $var wire  8 p# seg7_seg [7:0] $end
   $var wire  8 q# seg7_seg1 [7:0] $end
   $var wire  8 r# seg7_select [7:0] $end
   $var wire 32 z# uart_baud [31:0] $end
   $scope module i_bridge $end
    $var wire  6 % HWInt [7:2] $end
    $var wire  1 [! IORead $end
    $var wire  1 Z! IOWrite $end
    $var wire 30 I# PrAddr [31:2] $end
    $var wire  4 6# PrBE [3:0] $end
    $var wire 32 c PrRD [31:0] $end
    $var wire 32 J# PrWD [31:0] $end
    $var wire  1 m# clk $end
   $upscope $end
   $scope module mips $end
    $var wire  1 m# clk $end
    $var wire  1 n# rst $end
    $scope module i_branchCorrect $end
     $var wire  1 m# clk $end
     $var wire  1 K# correctAtEX $end
     $var wire  1 L# correctAtMEM $end
     $var wire 30 H! correctPCAtEX [31:2] $end
     $var wire 30 I! correctPCAtMEM [31:2] $end
    $upscope $end
    $scope module i_bridge $end
     $var wire  6 % HWInt [7:2] $end
     $var wire  1 [! IORead $end
     $var wire  1 Z! IOWrite $end
     $var wire 30 I# PrAddr [31:2] $end
     $var wire  4 6# PrBE [3:0] $end
     $var wire 32 c PrRD [31:0] $end
     $var wire 32 J# PrWD [31:0] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_bypass $end
     $var wire 38 E MEM_BACK [37:0] $end
     $var wire 32 I MEM_EXT_MEMout [31:0] $end
     $var wire  1 J MEM_memToReg $end
     $var wire 38 ?# WB_BACK [37:0] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_controller $end
     $var wire 19 "# EX_CTRL [18:0] $end
     $var wire  1 {# EX_FLUSH $end
     $var wire  9 k# ID_CTRL [8:0] $end
     $var wire  1 Q# ID_FLUSH $end
     $var wire 32 S" ID_instr [31:0] $end
     $var wire  1 P# IF_CTRL [0:0] $end
     $var wire  1 u# IF_FLUSH $end
     $var wire  1 :" MEM_CTRL [0:0] $end
     $var wire  1 {# MEM_FLUSH $end
     $var wire  5 ## WB_CTRL [4:0] $end
     $var wire  1 #$ WB_FLUSH $end
     $var wire  1 m# clk $end
     $var wire  6 ^! func [5:0] $end
     $var wire  6 ]! op [31:26] $end
     $var wire  5 _! rs [25:21] $end
     $var wire  5 `! rt [20:16] $end
    $upscope $end
    $scope module i_cp0 $end
     $var wire  2 M# CP0_CTRL [1:0] $end
     $var wire 32 Q! CP0_TO_EX [31:0] $end
     $var wire 30 R EPC [31:2] $end
     $var wire 38 '# EX_TO_CP0 [37:0] $end
     $var wire 30 \! ID_PCP1 [31:2] $end
     $var wire  1 G! IntReq $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_ex_mem $end
     $var wire 32 D DMout [31:0] $end
     $var wire  1 C! EXBranchAvail $end
     $var wire  1 ;! MEM_CTRL [0:0] $end
     $var wire 67 =! MEM_DATA [66:0] $end
     $var wire  5 <! WB_CTRL [4:0] $end
     $var wire 65 @! branchCommit [64:0] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_id_ex $end
     $var wire 19 0! EX_CTRL [18:0] $end
     $var wire 158 2! EX_DATA [157:0] $end
     $var wire  1 :! IDBranchAvail $end
     $var wire  1 A MEM_CTRL [0:0] $end
     $var wire  5 1! WB_CTRL [4:0] $end
     $var wire 65 7! branchCommit [64:0] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_if_id $end
     $var wire 62 %# ID_DATA [61:0] $end
     $var wire 30 w# NPC [31:2] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_mem_wb $end
     $var wire  5 D! WB_CTRL [4:0] $end
     $var wire 37 E! WB_DATA [36:0] $end
     $var wire  1 m# clk $end
    $upscope $end
    $scope module i_stallDetect $end
     $var wire  1 L! Branch_EX $end
     $var wire  1 M! Branch_LOAD $end
     $var wire  1 @ EX_memToReg $end
     $var wire  1 .! EX_regWrite $end
     $var wire  5 -! EX_rw [4:0] $end
     $var wire  1 :" ID_memWrite $end
     $var wire  5 _! ID_rs [4:0] $end
     $var wire  5 `! ID_rt [4:0] $end
     $var wire  1 J! LOAD $end
     $var wire  1 K! LOAD_STORE_SAME $end
     $var wire  1 J MEM_memToReg $end
     $var wire  5 /! MEM_rw [4:0] $end
     $var wire  1 N! NFG_EX $end
     $var wire  1 O! NFG_LOAD $end
     $var wire  1 Q" NPCFromGPR $end
     $var wire  1 $# branch $end
     $var wire  1 P! branchCommitAtMEM $end
     $var wire  1 m# clk $end
     $var wire  1 l# stall $end
    $upscope $end
    $scope module u_CP0 $end
     $var wire  2 M# CP0_CTRL [1:0] $end
     $var wire 32 + Cause [31:0] $end
     $var wire 32 )# DIn [31:0] $end
     $var wire 32 Q! Dout [31:0] $end
     $var wire  1 ' EXL $end
     $var wire 38 '# EX_DATA [37:0] $end
     $var wire  1 O# ExlClr $end
     $var wire  1 N# ExlSet $end
     $var wire  6 % HWInt [7:2] $end
     $var wire 30 \! ID_PCP1 [31:2] $end
     $var wire  1 ( IE $end
     $var wire  6 & IM [15:10] $end
     $var wire 32 # PrID [31:0] $end
     $var wire 32 * SR [31:0] $end
     $var wire  5 *# Sel [4:0] $end
     $var wire  1 +# Wen $end
     $var wire  1 m# clk $end
     $var wire  6 ) hwint_pend [15:10] $end
     $var wire  1 n# rst $end
     $scope module i_bridge $end
      $var wire  6 % HWInt [7:2] $end
      $var wire  1 [! IORead $end
      $var wire  1 Z! IOWrite $end
      $var wire 30 I# PrAddr [31:2] $end
      $var wire  4 6# PrBE [3:0] $end
      $var wire 32 c PrRD [31:0] $end
      $var wire 32 J# PrWD [31:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_cp0 $end
      $var wire  2 M# CP0_CTRL [1:0] $end
      $var wire 32 Q! CP0_TO_EX [31:0] $end
      $var wire 30 R EPC [31:2] $end
      $var wire 38 '# EX_TO_CP0 [37:0] $end
      $var wire 30 \! ID_PCP1 [31:2] $end
      $var wire  1 G! IntReq $end
      $var wire  1 m# clk $end
     $upscope $end
    $upscope $end
    $scope module u_Controller $end
     $var wire  1 ;" ALUAdd $end
     $var wire  1 >" ALUAnd $end
     $var wire  1 |! ALUNor $end
     $var wire  1 =" ALUOr $end
     $var wire  1 @" ALURs $end
     $var wire  1 A" ALUSrc $end
     $var wire  1 <" ALUSub $end
     $var wire  1 ?" ALUXor $end
     $var wire  1 w! AND $end
     $var wire  1 6" Branch $end
     $var wire  1 4" CP0WB $end
     $var wire  1 5" CP0Write $end
     $var wire  1 {# EX_FLUSH $end
     $var wire  1 3" ExlClr $end
     $var wire  1 R# ExlSet $end
     $var wire  1 Q# ID_FLUSH $end
     $var wire  1 u# IF_FLUSH $end
     $var wire  1 9" LOAD $end
     $var wire  1 K" MDDIV $end
     $var wire  3 M" MDFunc [2:0] $end
     $var wire  1 -" MDHIWB $end
     $var wire  1 ." MDLOWB $end
     $var wire  1 J" MDMUL $end
     $var wire  1 L" MDSign $end
     $var wire  1 {# MEM_FLUSH $end
     $var wire  1 |! NOR $end
     $var wire  1 3" NPCFromEPC $end
     $var wire  1 Q" NPCFromGPR $end
     $var wire  1 y! OR $end
     $var wire  1 P# PCWrite $end
     $var wire  1 :" STORE $end
     $var wire  1 z! XOR $end
     $var wire  1 a! add $end
     $var wire  1 k! addi $end
     $var wire  1 l! addiu $end
     $var wire  1 u! addu $end
     $var wire  4 I" aluop [3:0] $end
     $var wire  1 x! andi $end
     $var wire  1 d! beq $end
     $var wire  1 (" bgez $end
     $var wire  1 &" bgtz $end
     $var wire  1 )" blez $end
     $var wire  1 '" bltz $end
     $var wire  1 %" bne $end
     $var wire  3 N" branchType [2:0] $end
     $var wire  1 m# clk $end
     $var wire  1 1" div $end
     $var wire  1 2" divu $end
     $var wire  1 3" eret $end
     $var wire  1 C" exsign $end
     $var wire  1 B" extop $end
     $var wire  6 ^! func [5:0] $end
     $var wire  1 E" isDMByte $end
     $var wire  1 F" isDMHalf $end
     $var wire  1 G" isLOADS $end
     $var wire  1 H" isSlt $end
     $var wire  1 h! j $end
     $var wire  1 i! jal $end
     $var wire  1 *" jalr $end
     $var wire  1 O" jmp $end
     $var wire  1 j! jr $end
     $var wire  1 o! lb $end
     $var wire  1 p! lbu $end
     $var wire  1 q! lh $end
     $var wire  1 r! lhu $end
     $var wire  1 g! lui $end
     $var wire  1 f! lw $end
     $var wire  1 9" memToReg $end
     $var wire  1 :" memWrite $end
     $var wire  1 4" mfc0 $end
     $var wire  1 -" mfhi $end
     $var wire  1 ." mflo $end
     $var wire  1 5" mtc0 $end
     $var wire  1 +" mthi $end
     $var wire  1 ," mtlo $end
     $var wire  1 /" mult $end
     $var wire  1 0" multu $end
     $var wire  6 ]! op [5:0] $end
     $var wire  1 c! ori $end
     $var wire  1 D" regDst $end
     $var wire  1 R" regWrite $end
     $var wire  1 n# reset $end
     $var wire  5 _! rs [4:0] $end
     $var wire  5 `! rt [4:0] $end
     $var wire  1 P" savePC $end
     $var wire  1 s! sb $end
     $var wire  1 t! sh $end
     $var wire  1 }! sll $end
     $var wire  1 ~! sllv $end
     $var wire  1 m! slt $end
     $var wire  1 n! slti $end
     $var wire  1 #" sra $end
     $var wire  1 $" srav $end
     $var wire  1 !" srl $end
     $var wire  1 "" srlv $end
     $var wire 32 , stallCnt [31:0] $end
     $var wire  1 b! sub $end
     $var wire  1 v! subu $end
     $var wire  1 e! sw $end
     $var wire  1 8" typeIA $end
     $var wire  1 6" typeIB $end
     $var wire  1 7" typeR $end
     $var wire  1 {! xori $end
     $scope module i_branchCorrect $end
      $var wire  1 m# clk $end
      $var wire  1 K# correctAtEX $end
      $var wire  1 L# correctAtMEM $end
      $var wire 30 H! correctPCAtEX [31:2] $end
      $var wire 30 I! correctPCAtMEM [31:2] $end
     $upscope $end
     $scope module i_controller $end
      $var wire 19 "# EX_CTRL [18:0] $end
      $var wire  1 {# EX_FLUSH $end
      $var wire  9 k# ID_CTRL [8:0] $end
      $var wire  1 Q# ID_FLUSH $end
      $var wire 32 S" ID_instr [31:0] $end
      $var wire  1 P# IF_CTRL [0:0] $end
      $var wire  1 u# IF_FLUSH $end
      $var wire  1 :" MEM_CTRL [0:0] $end
      $var wire  1 {# MEM_FLUSH $end
      $var wire  5 ## WB_CTRL [4:0] $end
      $var wire  1 #$ WB_FLUSH $end
      $var wire  1 m# clk $end
      $var wire  6 ^! func [5:0] $end
      $var wire  6 ]! op [31:26] $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
     $upscope $end
     $scope module i_cp0 $end
      $var wire  2 M# CP0_CTRL [1:0] $end
      $var wire 32 Q! CP0_TO_EX [31:0] $end
      $var wire 30 R EPC [31:2] $end
      $var wire 38 '# EX_TO_CP0 [37:0] $end
      $var wire 30 \! ID_PCP1 [31:2] $end
      $var wire  1 G! IntReq $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_stallDetect $end
      $var wire  1 L! Branch_EX $end
      $var wire  1 M! Branch_LOAD $end
      $var wire  1 @ EX_memToReg $end
      $var wire  1 .! EX_regWrite $end
      $var wire  5 -! EX_rw [4:0] $end
      $var wire  1 :" ID_memWrite $end
      $var wire  5 _! ID_rs [4:0] $end
      $var wire  5 `! ID_rt [4:0] $end
      $var wire  1 J! LOAD $end
      $var wire  1 K! LOAD_STORE_SAME $end
      $var wire  1 J MEM_memToReg $end
      $var wire  5 /! MEM_rw [4:0] $end
      $var wire  1 N! NFG_EX $end
      $var wire  1 O! NFG_LOAD $end
      $var wire  1 Q" NPCFromGPR $end
      $var wire  1 $# branch $end
      $var wire  1 P! branchCommitAtMEM $end
      $var wire  1 m# clk $end
      $var wire  1 l# stall $end
     $upscope $end
    $upscope $end
    $scope module u_EX $end
     $var wire 32 0# ALUB [31:0] $end
     $var wire 32 1# ALUC [31:0] $end
     $var wire  1 5 ALUSrc $end
     $var wire  1 0 CP0WB $end
     $var wire  1 1 CP0Write $end
     $var wire  1 S! EXBranchAvail $end
     $var wire 32 = EXTB [31:0] $end
     $var wire 32 R! EXout [31:0] $end
     $var wire  3 . MDFunc [2:0] $end
     $var wire  1 6 MDHIWB $end
     $var wire  1 7 MDLOWB $end
     $var wire  1 8 MDSign $end
     $var wire 30 9 PCP1 [31:2] $end
     $var wire 32 2# accessAddr [31:0] $end
     $var wire  4 - aluop [3:0] $end
     $var wire  1 > branchCommitAtEX $end
     $var wire  3 / branchType [2:0] $end
     $var wire  1 m# clk $end
     $var wire 32 -# f_rd1 [31:0] $end
     $var wire 32 .# f_rd2 [31:0] $end
     $var wire 32 /# f_rd2_for_MEM [31:0] $end
     $var wire 32 : instr [31:0] $end
     $var wire  1 3 isSlt $end
     $var wire 32 ; rd1 [31:0] $end
     $var wire 32 < rd2 [31:0] $end
     $var wire  1 2 regDst $end
     $var wire  1 n# rst $end
     $var wire  1 4 savePC $end
     $var wire  1 ,# zero $end
     $scope module ALU $end
      $var wire 32 -# A [31:0] $end
      $var wire 32 0# B [31:0] $end
      $var wire 32 1# C [31:0] $end
      $var wire  4 - F [3:0] $end
      $var wire  5 ? sa [4:0] $end
      $var wire 32 T! sll [31:0] $end
      $var wire 32 3# sllv [31:0] $end
      $var wire 32 V! sra [31:0] $end
      $var wire 32 5# srav [31:0] $end
      $var wire 32 U! srl [31:0] $end
      $var wire 32 4# srlv [31:0] $end
      $var wire 32 2# sum [31:0] $end
      $var wire  1 ,# zero $end
     $upscope $end
     $scope module i_branchCorrect $end
      $var wire  1 m# clk $end
      $var wire  1 K# correctAtEX $end
      $var wire  1 L# correctAtMEM $end
      $var wire 30 H! correctPCAtEX [31:2] $end
      $var wire 30 I! correctPCAtMEM [31:2] $end
     $upscope $end
     $scope module i_bridge $end
      $var wire  6 % HWInt [7:2] $end
      $var wire  1 [! IORead $end
      $var wire  1 Z! IOWrite $end
      $var wire 30 I# PrAddr [31:2] $end
      $var wire  4 6# PrBE [3:0] $end
      $var wire 32 c PrRD [31:0] $end
      $var wire 32 J# PrWD [31:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_bypass $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire 32 I MEM_EXT_MEMout [31:0] $end
      $var wire  1 J MEM_memToReg $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_controller $end
      $var wire 19 "# EX_CTRL [18:0] $end
      $var wire  1 {# EX_FLUSH $end
      $var wire  9 k# ID_CTRL [8:0] $end
      $var wire  1 Q# ID_FLUSH $end
      $var wire 32 S" ID_instr [31:0] $end
      $var wire  1 P# IF_CTRL [0:0] $end
      $var wire  1 u# IF_FLUSH $end
      $var wire  1 :" MEM_CTRL [0:0] $end
      $var wire  1 {# MEM_FLUSH $end
      $var wire  5 ## WB_CTRL [4:0] $end
      $var wire  1 #$ WB_FLUSH $end
      $var wire  1 m# clk $end
      $var wire  6 ^! func [5:0] $end
      $var wire  6 ]! op [31:26] $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
     $upscope $end
     $scope module i_cp0 $end
      $var wire  2 M# CP0_CTRL [1:0] $end
      $var wire 32 Q! CP0_TO_EX [31:0] $end
      $var wire 30 R EPC [31:2] $end
      $var wire 38 '# EX_TO_CP0 [37:0] $end
      $var wire 30 \! ID_PCP1 [31:2] $end
      $var wire  1 G! IntReq $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_ex_mem $end
      $var wire 32 D DMout [31:0] $end
      $var wire  1 C! EXBranchAvail $end
      $var wire  1 ;! MEM_CTRL [0:0] $end
      $var wire 67 =! MEM_DATA [66:0] $end
      $var wire  5 <! WB_CTRL [4:0] $end
      $var wire 65 @! branchCommit [64:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_id_ex $end
      $var wire 19 0! EX_CTRL [18:0] $end
      $var wire 158 2! EX_DATA [157:0] $end
      $var wire  1 :! IDBranchAvail $end
      $var wire  1 A MEM_CTRL [0:0] $end
      $var wire  5 1! WB_CTRL [4:0] $end
      $var wire 65 7! branchCommit [64:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_stallDetect $end
      $var wire  1 L! Branch_EX $end
      $var wire  1 M! Branch_LOAD $end
      $var wire  1 @ EX_memToReg $end
      $var wire  1 .! EX_regWrite $end
      $var wire  5 -! EX_rw [4:0] $end
      $var wire  1 :" ID_memWrite $end
      $var wire  5 _! ID_rs [4:0] $end
      $var wire  5 `! ID_rt [4:0] $end
      $var wire  1 J! LOAD $end
      $var wire  1 K! LOAD_STORE_SAME $end
      $var wire  1 J MEM_memToReg $end
      $var wire  5 /! MEM_rw [4:0] $end
      $var wire  1 N! NFG_EX $end
      $var wire  1 O! NFG_LOAD $end
      $var wire  1 Q" NPCFromGPR $end
      $var wire  1 $# branch $end
      $var wire  1 P! branchCommitAtMEM $end
      $var wire  1 m# clk $end
      $var wire  1 l# stall $end
     $upscope $end
     $scope module u_Access $end
      $var wire  1 7# AddrInDM $end
      $var wire  1 W! DMWrite $end
      $var wire 32 D DMout [31:0] $end
      $var wire 32 2# addr [31:0] $end
      $var wire  4 6# be [3:0] $end
      $var wire  1 m# clk $end
      $var wire 32 /# f_rd2 [31:0] $end
      $var wire  1 B isDMByte $end
      $var wire  1 C isDMHalf $end
      $var wire  1 @ memToReg $end
      $var wire  1 A memWrite $end
      $scope module U_BEEXT $end
       $var wire  4 6# be [3:0] $end
       $var wire  1 B isByte $end
       $var wire  1 C isHalf $end
       $var wire  2 8# low_addr [1:0] $end
      $upscope $end
      $scope module i_bridge $end
       $var wire  6 % HWInt [7:2] $end
       $var wire  1 [! IORead $end
       $var wire  1 Z! IOWrite $end
       $var wire 30 I# PrAddr [31:2] $end
       $var wire  4 6# PrBE [3:0] $end
       $var wire 32 c PrRD [31:0] $end
       $var wire 32 J# PrWD [31:0] $end
       $var wire  1 m# clk $end
      $upscope $end
      $scope module u_dm_ram $end
       $var wire 12 9# addra [13:2] $end
       $var wire  1 m# clka $end
       $var wire 32 ;# dina [31:0] $end
       $var wire 32 D douta [31:0] $end
       $var wire  1 7# ena $end
       $var wire  4 :# wea [3:0] $end
      $upscope $end
     $upscope $end
     $scope module u_BRANCH $end
      $var wire  1 =# SF $end
      $var wire  1 S! branchAvail $end
      $var wire  3 / branchType [2:0] $end
      $var wire  1 <# eq $end
      $var wire 32 -# rd1 [31:0] $end
      $var wire 32 .# rd2 [31:0] $end
      $var wire  1 ># zero $end
     $upscope $end
     $scope module u_EX_FORWARD $end
      $var wire  1 O AFromMEM $end
      $var wire  1 E# AFromWB $end
      $var wire  1 P BFromMEM $end
      $var wire  1 F# BFromWB $end
      $var wire  1 A EX_memWrite $end
      $var wire  1 Q LOADBFromWB $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire  1 N MEM_EN $end
      $var wire 32 I MEM_EXT_MEMout [31:0] $end
      $var wire 32 K MEM_Wd [31:0] $end
      $var wire  1 J MEM_memToReg $end
      $var wire  5 L MEM_rd [4:0] $end
      $var wire  1 M MEM_regWrite $end
      $var wire  1 |# USE_MEM_BACK $end
      $var wire  1 |# USE_WB_BACK $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 D# WB_EN $end
      $var wire 32 A# WB_Wd [31:0] $end
      $var wire  5 B# WB_rd [4:0] $end
      $var wire  1 C# WB_regWrite $end
      $var wire 32 -# f_rd1 [31:0] $end
      $var wire 32 .# f_rd2 [31:0] $end
      $var wire 32 /# f_rd2_for_MEM [31:0] $end
      $var wire  1 X! oriA $end
      $var wire  1 Y! oriB $end
      $var wire 32 ; rd1 [31:0] $end
      $var wire 32 < rd2 [31:0] $end
      $var wire  5 G rs [4:0] $end
      $var wire  5 H rt [4:0] $end
     $upscope $end
    $upscope $end
    $scope module u_ID $end
     $var wire 30 W" BPC [31:2] $end
     $var wire 32 v# EXTB [31:0] $end
     $var wire  1 U# ExlSet $end
     $var wire  1 ]# IDBranchAvail $end
     $var wire 30 V" NOJPC [31:2] $end
     $var wire  1 T# NPCFromEPC $end
     $var wire  1 W# NPCFromGPR $end
     $var wire 30 \! PCP1 [31:2] $end
     $var wire 32 A# WB_Wd [31:0] $end
     $var wire  1 C# WB_regWrite $end
     $var wire  5 B# WB_rw [4:0] $end
     $var wire  3 S# branchType [2:0] $end
     $var wire  1 m# clk $end
     $var wire  1 Y# exsign $end
     $var wire  1 X# extop $end
     $var wire 32 Z# f_rd1 [31:0] $end
     $var wire 32 [# f_rd2 [31:0] $end
     $var wire 32 S" instr [31:0] $end
     $var wire  1 V# jmp $end
     $var wire 32 [# nouse [31:0] $end
     $var wire  1 \# predictBranchAvail $end
     $var wire 32 T" rd1 [31:0] $end
     $var wire 32 U" rd2 [31:0] $end
     $var wire  1 n# rst $end
     $scope module EXT $end
      $var wire 16 X" A [15:0] $end
      $var wire 32 v# B [31:0] $end
      $var wire  1 Y# exsign $end
      $var wire  1 X# extop $end
     $upscope $end
     $scope module GPR $end
      $var wire 32 A# Wd [31:0] $end
      $var wire  1 m# clk $end
      $var wire 32 y" i [31:0] $end
      $var wire 32 T" rd1 [31:0] $end
      $var wire 32 U" rd2 [31:0] $end
      $var wire  1 C# regWrite $end
      $var wire 32 Y" register[0] [31:0] $end
      $var wire 32 c" register[10] [31:0] $end
      $var wire 32 d" register[11] [31:0] $end
      $var wire 32 e" register[12] [31:0] $end
      $var wire 32 f" register[13] [31:0] $end
      $var wire 32 g" register[14] [31:0] $end
      $var wire 32 h" register[15] [31:0] $end
      $var wire 32 i" register[16] [31:0] $end
      $var wire 32 j" register[17] [31:0] $end
      $var wire 32 k" register[18] [31:0] $end
      $var wire 32 l" register[19] [31:0] $end
      $var wire 32 Z" register[1] [31:0] $end
      $var wire 32 m" register[20] [31:0] $end
      $var wire 32 n" register[21] [31:0] $end
      $var wire 32 o" register[22] [31:0] $end
      $var wire 32 p" register[23] [31:0] $end
      $var wire 32 q" register[24] [31:0] $end
      $var wire 32 r" register[25] [31:0] $end
      $var wire 32 s" register[26] [31:0] $end
      $var wire 32 t" register[27] [31:0] $end
      $var wire 32 u" register[28] [31:0] $end
      $var wire 32 v" register[29] [31:0] $end
      $var wire 32 [" register[2] [31:0] $end
      $var wire 32 w" register[30] [31:0] $end
      $var wire 32 x" register[31] [31:0] $end
      $var wire 32 \" register[3] [31:0] $end
      $var wire 32 ]" register[4] [31:0] $end
      $var wire 32 ^" register[5] [31:0] $end
      $var wire 32 _" register[6] [31:0] $end
      $var wire 32 `" register[7] [31:0] $end
      $var wire 32 a" register[8] [31:0] $end
      $var wire 32 b" register[9] [31:0] $end
      $var wire  1 n# reset $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
      $var wire  5 B# rw [15:11] $end
     $upscope $end
     $scope module i_branchCorrect $end
      $var wire  1 m# clk $end
      $var wire  1 K# correctAtEX $end
      $var wire  1 L# correctAtMEM $end
      $var wire 30 H! correctPCAtEX [31:2] $end
      $var wire 30 I! correctPCAtMEM [31:2] $end
     $upscope $end
     $scope module i_bypass $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire 32 I MEM_EXT_MEMout [31:0] $end
      $var wire  1 J MEM_memToReg $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_controller $end
      $var wire 19 "# EX_CTRL [18:0] $end
      $var wire  1 {# EX_FLUSH $end
      $var wire  9 k# ID_CTRL [8:0] $end
      $var wire  1 Q# ID_FLUSH $end
      $var wire 32 S" ID_instr [31:0] $end
      $var wire  1 P# IF_CTRL [0:0] $end
      $var wire  1 u# IF_FLUSH $end
      $var wire  1 :" MEM_CTRL [0:0] $end
      $var wire  1 {# MEM_FLUSH $end
      $var wire  5 ## WB_CTRL [4:0] $end
      $var wire  1 #$ WB_FLUSH $end
      $var wire  1 m# clk $end
      $var wire  6 ^! func [5:0] $end
      $var wire  6 ]! op [31:26] $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
     $upscope $end
     $scope module i_cp0 $end
      $var wire  2 M# CP0_CTRL [1:0] $end
      $var wire 32 Q! CP0_TO_EX [31:0] $end
      $var wire 30 R EPC [31:2] $end
      $var wire 38 '# EX_TO_CP0 [37:0] $end
      $var wire 30 \! ID_PCP1 [31:2] $end
      $var wire  1 G! IntReq $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_id_ex $end
      $var wire 19 0! EX_CTRL [18:0] $end
      $var wire 158 2! EX_DATA [157:0] $end
      $var wire  1 :! IDBranchAvail $end
      $var wire  1 A MEM_CTRL [0:0] $end
      $var wire  5 1! WB_CTRL [4:0] $end
      $var wire 65 7! branchCommit [64:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_if_id $end
      $var wire 62 %# ID_DATA [61:0] $end
      $var wire 30 w# NPC [31:2] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_stallDetect $end
      $var wire  1 L! Branch_EX $end
      $var wire  1 M! Branch_LOAD $end
      $var wire  1 @ EX_memToReg $end
      $var wire  1 .! EX_regWrite $end
      $var wire  5 -! EX_rw [4:0] $end
      $var wire  1 :" ID_memWrite $end
      $var wire  5 _! ID_rs [4:0] $end
      $var wire  5 `! ID_rt [4:0] $end
      $var wire  1 J! LOAD $end
      $var wire  1 K! LOAD_STORE_SAME $end
      $var wire  1 J MEM_memToReg $end
      $var wire  5 /! MEM_rw [4:0] $end
      $var wire  1 N! NFG_EX $end
      $var wire  1 O! NFG_LOAD $end
      $var wire  1 Q" NPCFromGPR $end
      $var wire  1 $# branch $end
      $var wire  1 P! branchCommitAtMEM $end
      $var wire  1 m# clk $end
      $var wire  1 l# stall $end
     $upscope $end
     $scope module npc $end
      $var wire 30 W" BPC [31:2] $end
      $var wire 30 R EPC [31:2] $end
      $var wire 30 x# JPC [31:2] $end
      $var wire 30 V" NOJPC [31:2] $end
      $var wire 30 w# NPC [31:2] $end
      $var wire  1 T# NPCFromEPC $end
      $var wire  1 W# NPCFromGPR $end
      $var wire 30 \! PC [31:2] $end
      $var wire  1 \# branchAvail $end
      $var wire  1 U# goExceptionHandler $end
      $var wire 26 z" instr_index [27:2] $end
      $var wire  1 V# jmp $end
      $var wire  1 ^# jpcAvail $end
      $var wire 16 X" offset [17:2] $end
      $var wire 32 Z# reg_index [31:0] $end
     $upscope $end
     $scope module u_BRANCH $end
      $var wire  1 `# SF $end
      $var wire  1 ]# branchAvail $end
      $var wire  3 S# branchType [2:0] $end
      $var wire  1 _# eq $end
      $var wire 32 Z# rd1 [31:0] $end
      $var wire 32 [# rd2 [31:0] $end
      $var wire  1 a# zero $end
     $upscope $end
     $scope module u_ID_FORWARD $end
      $var wire  1 b# AFromMEM $end
      $var wire  1 c# AFromWB $end
      $var wire  1 e# BFromMEM $end
      $var wire  1 f# BFromWB $end
      $var wire  1 {# EX_memWrite $end
      $var wire  1 {# LOADBFromWB $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire  1 S MEM_EN $end
      $var wire 32 }# MEM_EXT_MEMout [31:0] $end
      $var wire 32 K MEM_Wd [31:0] $end
      $var wire  1 {# MEM_memToReg $end
      $var wire  5 L MEM_rd [4:0] $end
      $var wire  1 M MEM_regWrite $end
      $var wire  1 |# USE_MEM_BACK $end
      $var wire  1 |# USE_WB_BACK $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 G# WB_EN $end
      $var wire 32 A# WB_Wd [31:0] $end
      $var wire  5 B# WB_rd [4:0] $end
      $var wire  1 C# WB_regWrite $end
      $var wire 32 Z# f_rd1 [31:0] $end
      $var wire 32 [# f_rd2 [31:0] $end
      $var wire 32 [# f_rd2_for_MEM [31:0] $end
      $var wire  1 d# oriA $end
      $var wire  1 g# oriB $end
      $var wire 32 T" rd1 [31:0] $end
      $var wire 32 U" rd2 [31:0] $end
      $var wire  5 _! rs [4:0] $end
      $var wire  5 `! rt [4:0] $end
     $upscope $end
     $scope module u_branch_predict $end
      $var wire  3 S# branchType [2:0] $end
      $var wire  1 m# clk $end
      $var wire  1 T lastPredict $end
      $var wire  6 U lastPredictAddr [5:0] $end
      $var wire  2 V lastPredictTime [1:0] $end
      $var wire  6 {" low_addr [5:0] $end
      $var wire  1 \# predictBranchAvail $end
      $scope module i_branchCorrect $end
       $var wire  1 m# clk $end
       $var wire  1 K# correctAtEX $end
       $var wire  1 L# correctAtMEM $end
       $var wire 30 H! correctPCAtEX [31:2] $end
       $var wire 30 I! correctPCAtMEM [31:2] $end
      $upscope $end
      $scope module unnamedblk1 $end
       $var wire 32 $ i [31:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module u_IF $end
     $var wire 30 |" ID_PCP1 [31:2] $end
     $var wire 32 }" ID_instr [31:0] $end
     $var wire 30 |" IF_PC [31:2] $end
     $var wire 32 H# IF_instr [31:0] $end
     $var wire 30 h# NPC [31:2] $end
     $var wire  1 m# clk $end
     $var wire  1 ~" firstFetch $end
     $var wire  1 n# rst $end
     $scope module IM $end
      $var wire 14 i# addr [15:2] $end
      $var wire  1 P# ce $end
      $var wire  1 m# clk $end
      $var wire 11 j# index [10:0] $end
      $var wire 32 H# instruct [31:0] $end
      $scope module u_imrom $end
       $var wire 11 j# addra [12:2] $end
       $var wire  1 m# clka $end
       $var wire 32 }# dina [31:0] $end
       $var wire 32 H# douta [31:0] $end
       $var wire  1 P# ena $end
       $var wire  1 {# wea $end
      $upscope $end
     $upscope $end
     $scope module i_branchCorrect $end
      $var wire  1 m# clk $end
      $var wire  1 K# correctAtEX $end
      $var wire  1 L# correctAtMEM $end
      $var wire 30 H! correctPCAtEX [31:2] $end
      $var wire 30 I! correctPCAtMEM [31:2] $end
     $upscope $end
     $scope module i_controller $end
      $var wire 19 "# EX_CTRL [18:0] $end
      $var wire  1 {# EX_FLUSH $end
      $var wire  9 k# ID_CTRL [8:0] $end
      $var wire  1 Q# ID_FLUSH $end
      $var wire 32 S" ID_instr [31:0] $end
      $var wire  1 P# IF_CTRL [0:0] $end
      $var wire  1 u# IF_FLUSH $end
      $var wire  1 :" MEM_CTRL [0:0] $end
      $var wire  1 {# MEM_FLUSH $end
      $var wire  5 ## WB_CTRL [4:0] $end
      $var wire  1 #$ WB_FLUSH $end
      $var wire  1 m# clk $end
      $var wire  6 ^! func [5:0] $end
      $var wire  6 ]! op [31:26] $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
     $upscope $end
     $scope module i_if_id $end
      $var wire 62 %# ID_DATA [61:0] $end
      $var wire 30 w# NPC [31:2] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module pc $end
      $var wire 30 h# NPC [31:2] $end
      $var wire 30 |" PC [31:2] $end
      $var wire  1 P# PCWrite $end
      $var wire  1 m# clk $end
      $var wire 30 !# line [29:0] $end
      $var wire  1 n# reset $end
     $upscope $end
    $upscope $end
    $scope module u_MEM $end
     $var wire  1 \ AddrInDM $end
     $var wire 32 I EXT_MEMout [31:0] $end
     $var wire 32 W EXout [31:0] $end
     $var wire 32 ] MEMout [31:0] $end
     $var wire 32 ^ WB_Wd [31:0] $end
     $var wire  1 m# clk $end
     $var wire  1 Y isDMByte $end
     $var wire  1 Z isDMHalf $end
     $var wire  1 [ isLOADS $end
     $var wire  1 J memToReg $end
     $var wire  1 X regWrite $end
     $var wire  1 n# rst $end
     $scope module U_DREXT $end
      $var wire  1 [ exsign $end
      $var wire 16 b half [15:0] $end
      $var wire 32 ] in_data [31:0] $end
      $var wire  1 Y isByte $end
      $var wire  1 Z isHalf $end
      $var wire  2 _ low_addr [1:0] $end
      $var wire 32 I out_data [31:0] $end
      $var wire  5 ` shift_bit [4:0] $end
      $var wire 32 a shifted_data [31:0] $end
     $upscope $end
     $scope module i_branchCorrect $end
      $var wire  1 m# clk $end
      $var wire  1 K# correctAtEX $end
      $var wire  1 L# correctAtMEM $end
      $var wire 30 H! correctPCAtEX [31:2] $end
      $var wire 30 I! correctPCAtMEM [31:2] $end
     $upscope $end
     $scope module i_bridge $end
      $var wire  6 % HWInt [7:2] $end
      $var wire  1 [! IORead $end
      $var wire  1 Z! IOWrite $end
      $var wire 30 I# PrAddr [31:2] $end
      $var wire  4 6# PrBE [3:0] $end
      $var wire 32 c PrRD [31:0] $end
      $var wire 32 J# PrWD [31:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_bypass $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire 32 I MEM_EXT_MEMout [31:0] $end
      $var wire  1 J MEM_memToReg $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_controller $end
      $var wire 19 "# EX_CTRL [18:0] $end
      $var wire  1 {# EX_FLUSH $end
      $var wire  9 k# ID_CTRL [8:0] $end
      $var wire  1 Q# ID_FLUSH $end
      $var wire 32 S" ID_instr [31:0] $end
      $var wire  1 P# IF_CTRL [0:0] $end
      $var wire  1 u# IF_FLUSH $end
      $var wire  1 :" MEM_CTRL [0:0] $end
      $var wire  1 {# MEM_FLUSH $end
      $var wire  5 ## WB_CTRL [4:0] $end
      $var wire  1 #$ WB_FLUSH $end
      $var wire  1 m# clk $end
      $var wire  6 ^! func [5:0] $end
      $var wire  6 ]! op [31:26] $end
      $var wire  5 _! rs [25:21] $end
      $var wire  5 `! rt [20:16] $end
     $upscope $end
     $scope module i_ex_mem $end
      $var wire 32 D DMout [31:0] $end
      $var wire  1 C! EXBranchAvail $end
      $var wire  1 ;! MEM_CTRL [0:0] $end
      $var wire 67 =! MEM_DATA [66:0] $end
      $var wire  5 <! WB_CTRL [4:0] $end
      $var wire 65 @! branchCommit [64:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_mem_wb $end
      $var wire  5 D! WB_CTRL [4:0] $end
      $var wire 37 E! WB_DATA [36:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_stallDetect $end
      $var wire  1 L! Branch_EX $end
      $var wire  1 M! Branch_LOAD $end
      $var wire  1 @ EX_memToReg $end
      $var wire  1 .! EX_regWrite $end
      $var wire  5 -! EX_rw [4:0] $end
      $var wire  1 :" ID_memWrite $end
      $var wire  5 _! ID_rs [4:0] $end
      $var wire  5 `! ID_rt [4:0] $end
      $var wire  1 J! LOAD $end
      $var wire  1 K! LOAD_STORE_SAME $end
      $var wire  1 J MEM_memToReg $end
      $var wire  5 /! MEM_rw [4:0] $end
      $var wire  1 N! NFG_EX $end
      $var wire  1 O! NFG_LOAD $end
      $var wire  1 Q" NPCFromGPR $end
      $var wire  1 $# branch $end
      $var wire  1 P! branchCommitAtMEM $end
      $var wire  1 m# clk $end
      $var wire  1 l# stall $end
     $upscope $end
    $upscope $end
    $scope module u_WB $end
     $var wire  1 m# clk $end
     $var wire  1 n# rst $end
     $scope module i_bypass $end
      $var wire 38 E MEM_BACK [37:0] $end
      $var wire 32 I MEM_EXT_MEMout [31:0] $end
      $var wire  1 J MEM_memToReg $end
      $var wire 38 ?# WB_BACK [37:0] $end
      $var wire  1 m# clk $end
     $upscope $end
     $scope module i_mem_wb $end
      $var wire  5 D! WB_CTRL [4:0] $end
      $var wire 37 E! WB_DATA [36:0] $end
      $var wire  1 m# clk $end
     $upscope $end
    $upscope $end
   $upscope $end
   $scope module u_BRIDGE $end
    $var wire 32 y# ClkFrequency [31:0] $end
    $var wire 32 ~# DEV0_RD [31:0] $end
    $var wire 32 i DEV1_RD [31:0] $end
    $var wire 32 j DEV2_RD [31:0] $end
    $var wire 32 k DEV3_RD [31:0] $end
    $var wire 32 e DEV_WD [31:0] $end
    $var wire  6 % HWInt [7:2] $end
    $var wire  1 m HitDEV0 $end
    $var wire  1 n HitDEV1 $end
    $var wire  1 o HitDEV2 $end
    $var wire  1 p HitDEV3 $end
    $var wire  1 q IntDEV0 $end
    $var wire 30 d PrAddr [31:2] $end
    $var wire 30 I# PrAddrWire [31:2] $end
    $var wire  4 f PrBE [3:0] $end
    $var wire  4 6# PrBEWire [3:0] $end
    $var wire 32 c PrRD [31:0] $end
    $var wire 32 e PrWD [31:0] $end
    $var wire 32 J# PrWDWire [31:0] $end
    $var wire  1 h RdCPU $end
    $var wire  1 [! RdCPUWire $end
    $var wire  1 s# RxD $end
    $var wire  1 t# TxD $end
    $var wire  1 g WeCPU $end
    $var wire  1 Z! WeCPUWire $end
    $var wire  4 l WeDEV [3:0] $end
    $var wire  1 m# clk $end
    $var wire  8 o# o_led [7:0] $end
    $var wire  8 p# seg7_seg [7:0] $end
    $var wire  8 r# seg7_select [7:0] $end
    $var wire 32 z# uart_baud [31:0] $end
    $scope module U_screenBoard $end
     $var wire 32 e D [31:0] $end
     $var wire  1 r WE $end
     $var wire  1 m# clk $end
     $var wire 32 i show [31:0] $end
    $upscope $end
    $scope module u_counter $end
     $var wire 32 e D [31:0] $end
     $var wire  1 q INT $end
     $var wire  1 s WE $end
     $var wire  1 m# clk $end
     $var wire 32 t cnt [31:0] $end
    $upscope $end
    $scope module u_seg7 $end
     $var wire  1 u A $end
     $var wire 32 e D [31:0] $end
     $var wire 32 j Dout [31:0] $end
     $var wire  4 f be [3:0] $end
     $var wire  1 m# clk $end
     $var wire 19 y cnt [18:0] $end
     $var wire  3 { lightDig [2:0] $end
     $var wire  8 | newSeg [7:0] $end
     $var wire  8 } newSelect [7:0] $end
     $var wire 10 z pause [9:0] $end
     $var wire 32 w ram[0] [31:0] $end
     $var wire 32 x ram[1] [31:0] $end
     $var wire  8 p# seg [7:0] $end
     $var wire  8 r# select [7:0] $end
     $var wire  1 v we $end
    $upscope $end
    $scope module u_uart $end
     $var wire  1 u A $end
     $var wire 32 z# Baud [31:0] $end
     $var wire 32 y# ClkFrequency [31:0] $end
     $var wire 32 e Din [31:0] $end
     $var wire 32 k Dout [31:0] $end
     $var wire  1 s# RxD $end
     $var wire  1 #! RxD_clear $end
     $var wire  8 &! RxD_data [7:0] $end
     $var wire  1 $! RxD_data_ready $end
     $var wire  1 t# TxD $end
     $var wire  1 %! TxD_busy $end
     $var wire  1 "! TxD_start $end
     $var wire  1 m# clk $end
     $var wire  1 !! re $end
     $var wire  8 '! status [7:0] $end
     $var wire  1 ~ we $end
     $scope module u_async_receiver $end
      $var wire 32 z# Baud [31:0] $end
      $var wire 32 y# ClkFrequency [31:0] $end
      $var wire 32 !$ Oversampling [31:0] $end
      $var wire  1 s# RxD $end
      $var wire  1 s# RxD_bit $end
      $var wire  1 #! RxD_clear $end
      $var wire  8 &! RxD_data [7:0] $end
      $var wire  1 $! RxD_data_ready $end
      $var wire  1 "$ RxD_endofpacket $end
      $var wire  1 {# RxD_idle $end
      $var wire  4 (! RxD_state [3:0] $end
      $var wire  1 m# clk $end
      $var wire  1 |# sampleNow $end
     $upscope $end
     $scope module u_async_transmitter $end
      $var wire 32 z# Baud [31:0] $end
      $var wire  1 |# BitTick $end
      $var wire 32 y# ClkFrequency [31:0] $end
      $var wire  1 t# TxD $end
      $var wire  1 %! TxD_busy $end
      $var wire  8 )! TxD_data [7:0] $end
      $var wire  1 +! TxD_ready $end
      $var wire  8 ,! TxD_shift [7:0] $end
      $var wire  1 "! TxD_start $end
      $var wire  4 *! TxD_state [3:0] $end
      $var wire  1 m# clk $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end