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regdefs.h
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regdefs.h
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ./regdefs.h
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: autofpga autofpga -d -o . allclocks.txt global.txt icape.txt version.txt buserr.txt pic.txt pwrcount.txt spio.txt clrspio.txt rtcgps.txt rtcdate.txt wbuconsole.txt bkram.txt spansion.txt sdram.txt zipmaster.txt mdio.txt enet.txt gps.txt wboledrgb.txt mem_flash_bkram.txt mem_bkram_only.txt mem_sdram_bkram.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2020, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef REGDEFS_H
#define REGDEFS_H
//
// The @REGDEFS.H.INCLUDE tag
//
// @REGDEFS.H.INCLUDE for masters
// @REGDEFS.H.INCLUDE for peripherals
// And finally any master REGDEFS.H.INCLUDE tags
// End of definitions from REGDEFS.H.INCLUDE
//
// Register address definitions, from @REGS.#d
//
// FLASH erase/program configuration registers
#define R_FLASHCFG 0x01000000 // 01000000, wbregs names: FLASHCFG, QSPIC
// GPS UART registers, similar to WBUART
#define R_GPSU_SETUP 0x02000000 // 02000000, wbregs names: GPSSETUP
#define R_GPSU_FIFO 0x02000004 // 02000000, wbregs names: GPSFIFO
#define R_GPSU_UARTRX 0x02000008 // 02000000, wbregs names: GPSRX
#define R_GPSU_UARTTX 0x0200000c // 02000000, wbregs names: GPSTX
// CONSOLE registers
#define R_CONSOLE_FIFO 0x03000004 // 03000000, wbregs names: UFIFO
#define R_CONSOLE_UARTRX 0x03000008 // 03000000, wbregs names: RX
#define R_CONSOLE_UARTTX 0x0300000c // 03000000, wbregs names: TX
// FPGA CONFIG REGISTERS: 0x4e0-0x4ff
#define R_CFG_CRC 0x04000000 // 04000000, wbregs names: FPGACRC
#define R_CFG_FAR 0x04000004 // 04000000, wbregs names: FPGAFAR
#define R_CFG_FDRI 0x04000008 // 04000000, wbregs names: FPGAFDRI
#define R_CFG_FDRO 0x0400000c // 04000000, wbregs names: FPGAFDRO
#define R_CFG_CMD 0x04000010 // 04000000, wbregs names: FPGACMD
#define R_CFG_CTL0 0x04000014 // 04000000, wbregs names: FPGACTL0
#define R_CFG_MASK 0x04000018 // 04000000, wbregs names: FPGAMASK
#define R_CFG_STAT 0x0400001c // 04000000, wbregs names: FPGASTAT
#define R_CFG_LOUT 0x04000020 // 04000000, wbregs names: FPGALOUT
#define R_CFG_COR0 0x04000024 // 04000000, wbregs names: FPGACOR0
#define R_CFG_MFWR 0x04000028 // 04000000, wbregs names: FPGAMFWR
#define R_CFG_CBC 0x0400002c // 04000000, wbregs names: FPGACBC
#define R_CFG_IDCODE 0x04000030 // 04000000, wbregs names: FPGAIDCODE
#define R_CFG_AXSS 0x04000034 // 04000000, wbregs names: FPGAAXSS
#define R_CFG_COR1 0x04000038 // 04000000, wbregs names: FPGACOR1
#define R_CFG_WBSTAR 0x04000040 // 04000000, wbregs names: WBSTAR
#define R_CFG_TIMER 0x04000044 // 04000000, wbregs names: CFGTIMER
#define R_CFG_BOOTSTS 0x04000058 // 04000000, wbregs names: BOOTSTS
#define R_CFG_CTL1 0x04000060 // 04000000, wbregs names: FPGACTL1
#define R_CFG_BSPI 0x0400007c // 04000000, wbregs names: FPGABSPI
// Ethernet configuration (MDIO) port
#define R_MDIO_BMCR 0x05000000 // 05000000, wbregs names: BMCR
#define R_MDIO_BMSR 0x05000004 // 05000000, wbregs names: BMSR
#define R_MDIO_PHYIDR1 0x05000008 // 05000000, wbregs names: PHYIDR1
#define R_MDIO_PHYIDR2 0x0500000c // 05000000, wbregs names: PHYIDR2
#define R_MDIO_ANAR 0x05000010 // 05000000, wbregs names: ANAR
#define R_MDIO_ANLPAR 0x05000014 // 05000000, wbregs names: ANLPAR
#define R_MDIO_ANER 0x05000018 // 05000000, wbregs names: ANER
#define R_MDIO_ANNPTR 0x0500001c // 05000000, wbregs names: ANNPTR
#define R_MDIO_PHYSTS 0x05000040 // 05000000, wbregs names: PHYSYTS
#define R_MDIO_FCSCR 0x05000050 // 05000000, wbregs names: FCSCR
#define R_MDIO_RECR 0x05000054 // 05000000, wbregs names: RECR
#define R_MDIO_PCSR 0x05000058 // 05000000, wbregs names: PCSR
#define R_MDIO_RBR 0x0500005c // 05000000, wbregs names: RBR
#define R_MDIO_LEDCR 0x05000060 // 05000000, wbregs names: LEDCR
#define R_MDIO_PHYCR 0x05000064 // 05000000, wbregs names: PHYCR
#define R_MDIO_BTSCR 0x05000068 // 05000000, wbregs names: BTSCR
#define R_MDIO_CDCTRL 0x0500006c // 05000000, wbregs names: CDCTRL
#define R_MDIO_EDCR 0x05000074 // 05000000, wbregs names: EDCR
#define R_CLRLED 0x06000000 // 06000000, wbregs names: CLRLED
#define R_CLRLED0 0x06000000 // 06000000, wbregs names: CLRLED0, CLR0
#define R_CLRLED1 0x06000004 // 06000000, wbregs names: CLRLED1, CLR1
#define R_CLRLED2 0x06000008 // 06000000, wbregs names: CLRLED2, CLR2
#define R_CLRLED3 0x0600000c // 06000000, wbregs names: CLRLED3, CLR3
// GPS clock tracker, control loop settings registers
#define R_GPS_ALPHA 0x06000020 // 06000020, wbregs names: ALPHA
#define R_GPS_BETA 0x06000024 // 06000020, wbregs names: BETA
#define R_GPS_GAMMA 0x06000028 // 06000020, wbregs names: GAMMA
#define R_GPS_STEP 0x0600002c // 06000020, wbregs names: STEP
// OLEDRGB
#define R_OLEDRGB_CMD 0x06000040 // 06000040, wbregs names: OLEDRGB, OLED
#define R_OLEDRGB_CDATA 0x06000044 // 06000040, wbregs names: OLEDRGBA, OLEDCA
#define R_OLEDRGB_CDATB 0x06000048 // 06000040, wbregs names: OLEDRGBB, OLEDCB
#define R_OLEDRGB_DATA 0x0600004c // 06000040, wbregs names: OLEDRGBD, ODATA
// GPS clock test bench registers, for measuring the clock trackers performance
#define R_GPSTB_FREQ 0x06000060 // 06000060, wbregs names: GPSFREQ
#define R_GPSTB_JUMP 0x06000064 // 06000060, wbregs names: GPSJUMP
#define R_GPSTB_ERRHI 0x06000068 // 06000060, wbregs names: ERRHI
#define R_GPSTB_ERRLO 0x0600006c // 06000060, wbregs names: ERRLO
#define R_GPSTB_COUNTHI 0x06000070 // 06000060, wbregs names: CNTHI
#define R_GPSTB_COUNTLO 0x06000074 // 06000060, wbregs names: CNTLO
#define R_GPSTB_STEPHI 0x06000078 // 06000060, wbregs names: STEPHI
#define R_GPSTB_STEPLO 0x0600007c // 06000060, wbregs names: STEPLO
#define R_NET_RXCMD 0x06000080 // 06000080, wbregs names: RXCMD, NETRX
#define R_NET_TXCMD 0x06000084 // 06000080, wbregs names: TXCMD, NETTX
#define R_NET_MACHI 0x06000088 // 06000080, wbregs names: MACHI
#define R_NET_MACLO 0x0600008c // 06000080, wbregs names: MACLO
#define R_NET_RXMISS 0x06000090 // 06000080, wbregs names: NETMISS
#define R_NET_RXERR 0x06000094 // 06000080, wbregs names: NETERR
#define R_NET_RXCRC 0x06000098 // 06000080, wbregs names: NETCRCERR
#define R_NET_TXCOL 0x0600009c // 06000080, wbregs names: NETCOL
// RTC clock registers
#define R_CLOCK 0x060000a0 // 060000a0, wbregs names: CLOCK
#define R_TIMER 0x060000a4 // 060000a0, wbregs names: TIMER
#define R_STOPWATCH 0x060000a8 // 060000a0, wbregs names: STOPWATCH
#define R_CKALARM 0x060000ac // 060000a0, wbregs names: ALARM, CKALARM
#define R_BUILDTIME 0x060000c0 // 060000c0, wbregs names: BUILDTIME
#define R_BUSERR 0x060000c4 // 060000c4, wbregs names: BUSERR
#define R_PIC 0x060000c8 // 060000c8, wbregs names: PIC
#define R_PWRCOUNT 0x060000cc // 060000cc, wbregs names: PWRCOUNT
#define R_RTCDATE 0x060000d0 // 060000d0, wbregs names: RTCDATE, DATE
#define R_SPIO 0x060000d4 // 060000d4, wbregs names: SPIO
// A register capturing subseconds, locked to GPS if present
#define R_SUBSECONDS 0x060000d8 // 060000d8, wbregs names: SUBSECONDS
#define R_VERSION 0x060000dc // 060000dc, wbregs names: VERSION
#define R_NET_RXBUF 0x07000000 // 07000000, wbregs names: NETRXB
#define R_NET_TXBUF 0x07001000 // 07000000, wbregs names: NETTXB
#define R_BKRAM 0x08000000 // 08000000, wbregs names: RAM
#define R_FLASH 0x09000000 // 09000000, wbregs names: FLASH
#define R_SDRAM 0x10000000 // 10000000, wbregs names: SDRAM
//
// The @REGDEFS.H.DEFNS tag
//
// @REGDEFS.H.DEFNS for masters
#define ENETCLKFREQHZ 25000000
#define R_ZIPCTRL 0x20000000
#define R_ZIPDATA 0x20000004
// #define RESET_ADDRESS @$[0x%08x](RESET_ADDRESS)
#define BAUDRATE 1000000
#define CLKFREQHZ 82500000
// @REGDEFS.H.DEFNS for peripherals
#define SDRAMBASE 0x10000000
#define SDRAMLEN 0x10000000
#define FLASHBASE 0x09000000
#define FLASHLEN 0x01000000
#define FLASHLGLEN 24
//
#define FLASH_RDDELAY 3
#define FLASH_NDUMMY 6
//
#define BKRAMBASE 0x08000000
#define BKRAMLEN 0x00010000
// @REGDEFS.H.DEFNS at the top level
// End of definitions from REGDEFS.H.DEFNS
//
// The @REGDEFS.H.INSERT tag
//
// @REGDEFS.H.INSERT for masters
// @REGDEFS.H.INSERT for peripherals
#define CPU_GO 0x0000
#define CPU_RESET 0x0040
#define CPU_INT 0x0080
#define CPU_STEP 0x0100
#define CPU_STALL 0x0200
#define CPU_HALT 0x0400
#define CPU_CLRCACHE 0x0800
#define CPU_sR0 0x0000
#define CPU_sSP 0x000d
#define CPU_sCC 0x000e
#define CPU_sPC 0x000f
#define CPU_uR0 0x0010
#define CPU_uSP 0x001d
#define CPU_uCC 0x001e
#define CPU_uPC 0x001f
#ifdef BKROM_ACCESS
#define RESET_ADDRESS @$[0x%08x](bkrom.REGBASE)
#else
#ifdef FLASH_ACCESS
#define RESET_ADDRESS 0x09400000
#else
#define RESET_ADDRESS 0x08000000
#endif // FLASH_ACCESS
#endif // BKROM_ACCESS
// Flash control constants
#define QSPI_FLASH // This core and hardware support a Quad SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
// @REGDEFS.H.INSERT from the top level
typedef struct {
unsigned m_addr;
const char *m_name;
} REGNAME;
extern const REGNAME *bregs;
extern const int NREGS;
// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
extern unsigned addrdecode(const char *v);
extern const char *addrname(const unsigned v);
// End of definitions from REGDEFS.H.INSERT
#endif // REGDEFS_H