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zuluscsi_timings.ini
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zuluscsi_timings.ini
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[settings]
disable = False # True: disable custom settings - default false: use the settings of this file
# extends_speed_grade lets you choose a built in timing setting as a template
# this is the same value as would be set as SpeedGrade in zuluscsi.ini
# this allows the ability to use a minimum of the below settings in your zuluscsi_timings.ini file
extends_speed_grade = Default # Default, TurboMax, TurboA, TurboB, etc
# boot_with_sync value setting starts the board at an assumed sync value
# boot_with_offset value setting starts the board at an assumed offset value
# these are values are usually requested by the host to negotiate sync transfers
# this is for users who are restarting their boards while the system is running
# to test their settings and don't want to reboot their computers to renegotiate sync
# if a USB serial console is used, settings can be change using the key presses 'm' then 'y'
# for rebooting in mass storage mode, making changes to 'zuluscsi_timings.ini' then
# ejecting the mass storage device
# ** hot swapping like this is not recommended **
# the sync value is explained below
boot_with_sync_value = 0 # default value is 0 meaning this feature is off
boot_with_offset_value = 15 # default value and max value is 15, if boot_with_sync_value is 0 this value is
clk_hz = 250000000 # reclock target system frequency in Hz
[pll]
# These values can be found by using the script from the Pico-SDK:
# pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py
refdiv = 1 # reference divider
vco_freq_hz = 1500000000 # vco frequency in Hz
pd1 = 6 # Post divider 1
pd2 = 1 # Post divider 2
[scsi]
# Period of the system clock in picoseconds
clk_period_ps = 4000 # 1 / clk_hz * 10^12
# Delay from data setup to REQ assertion.
# deskew delay + cable skew delay = 55 ns minimum
req_delay_cc = 14 # 55ns / clk_period_ps * 1000 rounded up
# The next settings are for different SCSI synchronous clock speeds
# delay0: Data Setup Time - Delay from data write to REQ assertion
# delay1: Transmit Assertion time from REQ assert to REQ deassert (req pulse)
# delay2: Negation period - this value is calculated by the firmware: (total_delay - d0 - d1)
# total_delay spec is the sync value * 4 in ns
# Delay0 and Delay1 values are in clock cycles minus 1 for the pio instruction delay
# SCSI clock: Ultra(20) Fast(10) SCSI-1(5)
# delay0 spec: 11.5ns 23ns 23ns
# delay1 spec: 16.5ns 33ns 53ns
# delay2 spec: min 15ns min 30ns min 80ns
# total_delay_adjust is manual adjustment value, when checked with a scope
# sync value is what the SCSI controller sends to the device to negotiate it' sync speed
# These are the fastest sync values for each synchronous clock speed
# 12 (48ns) is for Fast20 21MB/s
# 25 (100ns) is for Fast10 10MB/s
# 50 (200ns) is for Fast5 5MB/s
# max_sync - the minimum sync period ("max" meaning fastest throughput) that
# is supported at this clock rate, the throughput is 1/4 the actual value in ns
# the max transfer speed is 1 / (4 * max_sync) in MB/s
# Though the ZuluSCSI generally isn't able to achieve that, it can get close on reads
# the maximum value that delay0_cc and delay1_cc can be set to is 15
# due to the way the Programmable IO on the RP2 series chips work
[scsi_20]
# These are the Ultra (Fast 20) synchronous SCSI settings, SCSI running at 20MHz
delay0_cc = 2 # 3 - 1 - delay 0 in clock cycles minus 1
delay1_cc = 4 # 5 - 1 - delay 1 in clock cycles minus 1
total_delay_adjust_cc = 1 # adjustment to the total sync period in clock cylces
max_sync = 12 # the max sync supported by the board in Fast20, total sync periods in ns / 4
[scsi_10]
# These are the Fast (Fast 10) synchronous SCSI settings, SCSI runnings at 10MHz
delay0_cc = 5 # 6 - 1
delay1_cc = 8 # 9 - 1
total_delay_adjust_cc = 1
max_sync = 25
[scsi_5]
# These are the SCSI-1 (Fast 5) synchronous SCSI settings, SCSI runnings at 5MHz
delay0_cc = 15 # maxed out, should probably be around 16
delay1_cc = 15 # maxed out, should probably be around be 30
total_delay_adjust_cc = 1
max_sync = 50
[sdio]
# These settings determine the clock setting and duty cycle of the SDIO clock
clk_div_pio = 5 # clk_hz / clk_div_pio should be between 25MHz and 50MHz
# SDIO first communicates to the SD card at 1MHz, clk_div_1mhz divides the SDIO clock down to 1MHz
clk_div_1mhz = 50 # this should be the SDIO clock speed in MHz, but for some SDIO clockspeeds using a smaller value worked
# delay0 and delay1 determine the duty cycle of the SDIO clock
# their total should equal clk_div_pio. but they both have 1 subtracted from
# them to accommodate the clock cycle a PIO instruction takes
# their max value is 15
delay0 = 3 # 4 - 1
delay1 = 0 # 1 - 1
# Please post your findings to https://github.com/ZuluSCSI/ZuluSCSI-firmware/discussions