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Can't unindent automatically for Verilog files #8980
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@vfraloo I've marked this as a low priority because our focus is on core web languages (HTML, JavaScript and CSS). If there's something we're doing differently from CodeMirror that we could reasonably improve, we'd take a pull request for this... |
@dangoor It's actually an issue with setting I tested XML and indeed, when the pref So this could have a bigger impact on Brackets and we should consider using CM's own electric char management. |
Raising priority since @marcelgerber found a more common use case. |
FYI @JeffryBooher, a fix is already in progress, but as it involves much testing and stuff, I assume it'll be ready in a week or so. |
Thanks @marcelgerber! |
@vfraloo Hii.. Changes has been merged into master. Can you please verify and close the issue if fixed.. |
Verified. Indentation is working fine.. Closing.. |
I actived the verilog language mode of CodeMirror by following code, and it can works well.
But only one problem is that, brackets can't unindent automatically when I type some keywords like "end", "endtask", "endfunction", etc, which were suppost to be.
And I tried with CodeMirror's demo, it can works correctly. So I think there may be an issue or I made some mistakes.
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