From 0ac340e2cb4f3d6c139db7a66da3154ea23f50ad Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Wed, 2 Oct 2024 20:47:31 -0700 Subject: [PATCH 1/3] import package item fix for synlig --- .vscode/launch.json | 38 +++++ include/Surelog/DesignCompile/UhdmWriter.h | 1 + src/DesignCompile/UhdmWriter.cpp | 143 +++++++++++++++--- tests/AssignSubs/AssignSubs.log | 4 +- .../BlockingAssignRewrite.log | 2 - tests/EarlgreyPackParam/EarlgreyPackParam.log | 2 +- tests/EnumConstConcat/EnumConstConcat.log | 2 +- tests/LogicArrayParam/LogicArrayParam.log | 2 +- tests/MultiConcat/MultiConcat.log | 2 +- tests/OneImport/OneImport.log | 12 -- tests/PackDataType/PackDataType.log | 2 +- tests/PackStructVar/PackStructVar.log | 2 +- tests/ParamConstPush/ParamConstPush.log | 2 +- tests/ParamOverload3/ParamOverload3.log | 2 +- tests/ParamRef/ParamRef.log | 2 +- tests/StructVar/StructVar.log | 22 ++- third_party/tests/AzadiRTL/AzadiRTL.log | 8 +- third_party/tests/CoresSweRV/CoresSweRV.log | 4 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 16 +- .../Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log | 4 +- .../Earlgrey_Verilator_01_05_21.log | 8 +- .../sim-verilator/Earlgrey_Verilator_0_1.log | 4 +- third_party/tests/Ibex/Ibex.log | 2 +- third_party/tests/IncompTitan/IncompTitan.log | 2 +- .../tests/NyuziProcessor/NyuziProcessor.log | 4 +- third_party/tests/Opentitan/Earlgrey.log | 4 +- third_party/tests/Opentitan/Opentitan.log | 4 +- 27 files changed, 218 insertions(+), 82 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index edbf06c49e..3f13a84951 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -889,6 +889,44 @@ } ] }, + { + "name": "ScratchPad_NoUHDMElab", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/dbuild/bin/surelog", + "args": ["-parse", "tests/ScratchPad.sv", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nobuiltin"], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + }, + { + "name": "kmac", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/dbuild/bin/surelog", + "args": ["-parse", "sha3_pkg.sv", "kmac_core.sv", "kmac.sv", "-top", "kmac", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-elabuhdm", "-nobuiltin"], + "stopAtEntry": false, + "cwd": "/home/alain/os-fpga/Raptor/tests/Testcases/kmac", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + }, { "name": "ScratchPad_v", "type": "cppdbg", diff --git a/include/Surelog/DesignCompile/UhdmWriter.h b/include/Surelog/DesignCompile/UhdmWriter.h index 3618aec017..b37b92e0b4 100644 --- a/include/Surelog/DesignCompile/UhdmWriter.h +++ b/include/Surelog/DesignCompile/UhdmWriter.h @@ -84,6 +84,7 @@ class UhdmWriter final { void writeDataTypes(const DesignComponent::DataTypeMap& datatypeMap, UHDM::BaseClass* parent, UHDM::VectorOftypespec* dest_typespecs, UHDM::Serializer& s, bool setParent); + void writeImportedSymbols(DesignComponent* mod, UHDM::Serializer& s, UHDM::VectorOftypespec* typespecs); void writeVariables(const DesignComponent::VariableMap& orig_vars, UHDM::BaseClass* parent, UHDM::VectorOfvariables* dest_vars, UHDM::Serializer& s); diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index b9abb0bd9e..49401dd735 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -1075,12 +1075,10 @@ void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s, VectorOftypespec* typespecs = s.MakeTypespecVec(); p->Typespecs(typespecs); writeDataTypes(pack->getDataTypeMap(), p, typespecs, s, true); + writeImportedSymbols(pack, s, typespecs); for (auto tp : *typespecs) { tp->Instance(p); } - for (auto item : pack->getImportedSymbols()) { - typespecs->push_back(item); - } // Classes ClassNameClassDefinitionMultiMap& orig_classes = pack->getClassDefinitions(); dest_classes = s.MakeClass_defnVec(); @@ -1194,6 +1192,101 @@ void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s, lateBinding(s, pack, p); } +void UhdmWriter::writeImportedSymbols(DesignComponent* mod, Serializer& s, + VectorOftypespec* typespecs) { + for (auto item : mod->getImportedSymbols()) { + bool append = true; + for (auto tpsiter : *typespecs) { + if (item->VpiName() == tpsiter->VpiName()) { + append = false; + break; + } + } + if (append) { // Prevents multiple definition + typespecs->push_back(item); + } + constant* c = item->Item(); + if (c) { + std::string_view packName = item->VpiName(); + std::string_view typeName = c->VpiDecompile(); + Package* pack = + m_compileDesign->getCompiler()->getDesign()->getPackage(packName); + if (pack) { + const auto& itr = m_componentMap.find(pack); + if (itr != m_componentMap.end()) { + package* p = (package*)itr->second; + typespec* tps = nullptr; + enum_const* cts = nullptr; + if (p->Typespecs()) { + for (auto n : *p->Typespecs()) { + if (n->VpiName() == typeName) { + tps = n; + break; + } + const std::string pname = StrCat(p->VpiName(), "::", typeName); + if (n->VpiName() == pname) { + tps = n; + break; + } + if (n->UhdmType() == uhdmenum_typespec) { + enum_typespec* tpsiter = any_cast(n); + if (tpsiter && tpsiter->Enum_consts()) { + for (auto c : *tpsiter->Enum_consts()) { + if (c->VpiName() == typeName) { + cts = c; + tps = tpsiter; + break; + } + if (pname == c->VpiName()) { + cts = c; + tps = tpsiter; + break; + } + } + } + } + if (cts) break; + } + } + if (cts) { + // Ideally we would want to import only the given symbol, + // But Synlig does not process that properly, so instead we import + // the whole enum + bool append = true; + for (auto tpsiter : *typespecs) { + if (tps->VpiName() == tpsiter->VpiName()) { + append = false; + break; + } + } + if (append) { // Prevents multiple definition + ElaboratorContext elaboratorContext(&s, false, true); + typespec* item = + (typespec*)UHDM::clone_tree(tps, &elaboratorContext); + typespecs->push_back(item); + } + } else if (tps) { + bool append = true; + for (auto tpsiter : *typespecs) { + if (tps->VpiName() == tpsiter->VpiName()) { + append = false; + break; + } + } + if (append) { // Prevents multiple definition + ElaboratorContext elaboratorContext(&s, false, true); + typespec* item = + (typespec*)UHDM::clone_tree(tps, &elaboratorContext); + item->VpiName(typeName); + typespecs->push_back(item); + } + } + } + } + } + } +} + void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m, Serializer& s, ModuleMap& moduleMap, ModPortMap& modPortMap, ModuleInstance* instance) { @@ -1240,9 +1333,7 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // Ports std::vector& orig_ports = mod->getPorts(); VectorOfport* dest_ports = s.MakePortVec(); @@ -1465,9 +1556,7 @@ void UhdmWriter::writeInterface(ModuleDefinition* mod, interface_inst* m, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // Ports std::vector& orig_ports = mod->getPorts(); VectorOfport* dest_ports = s.MakePortVec(); @@ -1604,9 +1693,7 @@ void UhdmWriter::writeProgram(Program* mod, program* m, Serializer& s, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // Ports std::vector& orig_ports = mod->getPorts(); VectorOfport* dest_ports = s.MakePortVec(); @@ -1732,9 +1819,7 @@ bool UhdmWriter::writeElabProgram(Serializer& s, ModuleInstance* instance, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // Assertions if (mod->getAssertions()) { m->Assertions(mod->getAssertions()); @@ -2137,9 +2222,7 @@ bool UhdmWriter::writeElabGenScope(Serializer& s, ModuleInstance* instance, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // System elab tasks m->Elab_tasks((std::vector*)&mod->getElabSysCalls()); if (m->Elab_tasks()) { @@ -3606,7 +3689,9 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { const any* lhs = p->Lhs(); if (lhs->VpiName() == name) { // Do not bind blindly here, let the uhdmelab do this correctly - // ref->Actual_group((any*)p->Rhs()); + // Unless we are in a package + if (m && m->UhdmType() == uhdmpackage) + ref->Actual_group((any*)p->Rhs()); isParam = true; break; } @@ -3736,6 +3821,18 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { } } + if (!ref->Actual_group()) { + Value* value = mod->getValue(name); + if (value && value->isValid()) { + enum_const* c = s.MakeEnum_const(); + c->VpiName(name); + c->VpiValue(value->uhdmValue()); + c->VpiDecompile(value->decompiledValue()); + c->VpiSize(value->getSize()); + c->VpiParent(ref); + ref->Actual_group(c); + } + } if (!ref->Actual_group()) { if (mod) { if (auto elem = mod->getDesignElement()) { @@ -3813,9 +3910,7 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // System elab tasks m->Elab_tasks((std::vector*)&mod->getElabSysCalls()); if (m->Elab_tasks()) { @@ -3963,9 +4058,7 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance, VectorOftypespec* typespecs = s.MakeTypespecVec(); m->Typespecs(typespecs); writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false); - for (auto item : mod->getImportedSymbols()) { - typespecs->push_back(item); - } + writeImportedSymbols(mod, s, typespecs); // System elab tasks m->Elab_tasks((std::vector*)&mod->getElabSysCalls()); if (m->Elab_tasks()) { diff --git a/tests/AssignSubs/AssignSubs.log b/tests/AssignSubs/AssignSubs.log index ab5fdc317c..8835ae35cc 100644 --- a/tests/AssignSubs/AssignSubs.log +++ b/tests/AssignSubs/AssignSubs.log @@ -187,7 +187,7 @@ begin 3 bit_select 2 constant 27 design 1 -enum_const 2 +enum_const 3 enum_typespec 2 event_control 2 gen_for 1 @@ -220,7 +220,7 @@ begin 4 bit_select 3 constant 27 design 1 -enum_const 2 +enum_const 3 enum_typespec 2 event_control 3 gen_for 1 diff --git a/tests/BlockingAssignRewrite/BlockingAssignRewrite.log b/tests/BlockingAssignRewrite/BlockingAssignRewrite.log index 698428a979..2f27e890b2 100644 --- a/tests/BlockingAssignRewrite/BlockingAssignRewrite.log +++ b/tests/BlockingAssignRewrite/BlockingAssignRewrite.log @@ -1023,8 +1023,6 @@ ref_obj 106 ref_typespec 95 ref_var 2 === UHDM Object Stats End === -Converting blocking to non-blocking assignment to enable RAM inference for RAM -Converting blocking to non-blocking assignment to enable RAM inference for RAM [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ... [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/checker/surelog.chk.html ... [INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ... diff --git a/tests/EarlgreyPackParam/EarlgreyPackParam.log b/tests/EarlgreyPackParam/EarlgreyPackParam.log index 28c010d6f8..a8070fba16 100644 --- a/tests/EarlgreyPackParam/EarlgreyPackParam.log +++ b/tests/EarlgreyPackParam/EarlgreyPackParam.log @@ -2351,5 +2351,5 @@ design: (work@test) [ NOTE] : 7 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv | ${SURELOG_DIR}/build/regression/EarlgreyPackParam/roundtrip/dut_000.sv | 27 | 60 | +[roundtrip]: ${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv | ${SURELOG_DIR}/build/regression/EarlgreyPackParam/roundtrip/dut_000.sv | 28 | 60 | ============================== End RoundTrip Results ============================== diff --git a/tests/EnumConstConcat/EnumConstConcat.log b/tests/EnumConstConcat/EnumConstConcat.log index ed76bec914..5d6450be8d 100644 --- a/tests/EnumConstConcat/EnumConstConcat.log +++ b/tests/EnumConstConcat/EnumConstConcat.log @@ -622,5 +622,5 @@ design: (work@top) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/EnumConstConcat/dut.sv | ${SURELOG_DIR}/build/regression/EnumConstConcat/roundtrip/dut_000.sv | 3 | 28 | +[roundtrip]: ${SURELOG_DIR}/tests/EnumConstConcat/dut.sv | ${SURELOG_DIR}/build/regression/EnumConstConcat/roundtrip/dut_000.sv | 4 | 28 | ============================== End RoundTrip Results ============================== diff --git a/tests/LogicArrayParam/LogicArrayParam.log b/tests/LogicArrayParam/LogicArrayParam.log index d0d28a7374..b5b4337426 100644 --- a/tests/LogicArrayParam/LogicArrayParam.log +++ b/tests/LogicArrayParam/LogicArrayParam.log @@ -3964,5 +3964,5 @@ design: (work@alert_handler) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/LogicArrayParam/dut.sv | ${SURELOG_DIR}/build/regression/LogicArrayParam/roundtrip/dut_000.sv | 9 | 32 | +[roundtrip]: ${SURELOG_DIR}/tests/LogicArrayParam/dut.sv | ${SURELOG_DIR}/build/regression/LogicArrayParam/roundtrip/dut_000.sv | 10 | 32 | ============================== End RoundTrip Results ============================== diff --git a/tests/MultiConcat/MultiConcat.log b/tests/MultiConcat/MultiConcat.log index a60461b78b..c8f5b8a62f 100644 --- a/tests/MultiConcat/MultiConcat.log +++ b/tests/MultiConcat/MultiConcat.log @@ -7768,5 +7768,5 @@ design: (unnamed) [ NOTE] : 4 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/MultiConcat/dut.sv | ${SURELOG_DIR}/build/regression/MultiConcat/roundtrip/dut_000.sv | 37 | 172 | +[roundtrip]: ${SURELOG_DIR}/tests/MultiConcat/dut.sv | ${SURELOG_DIR}/build/regression/MultiConcat/roundtrip/dut_000.sv | 40 | 172 | ============================== End RoundTrip Results ============================== diff --git a/tests/OneImport/OneImport.log b/tests/OneImport/OneImport.log index 690674beba..b15d0ba6f5 100644 --- a/tests/OneImport/OneImport.log +++ b/tests/OneImport/OneImport.log @@ -491,12 +491,6 @@ design: (work@dut) \_enum_typespec: (my_pkg::opcode_e), line:2:3, endln:5:14 |vpiTypedef: \_import_typespec: (my_pkg), line:12:10, endln:12:19 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:10, endln:13:26 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:28, endln:13:47 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:28, endln:13:47 |vpiDefName:work@dut |vpiNet: \_logic_net: (work@dut.a), line:16:14, endln:16:15 @@ -665,12 +659,6 @@ design: (work@dut) \_enum_typespec: (my_pkg::opcode_e), line:2:3, endln:5:14 |vpiTypedef: \_import_typespec: (my_pkg), line:12:10, endln:12:19 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:10, endln:13:26 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:28, endln:13:47 - |vpiTypedef: - \_import_typespec: (my_pkg), line:13:28, endln:13:47 |vpiDefName:work@dut |vpiTop:1 |vpiNet: diff --git a/tests/PackDataType/PackDataType.log b/tests/PackDataType/PackDataType.log index 117f0f4b91..a967af16e3 100644 --- a/tests/PackDataType/PackDataType.log +++ b/tests/PackDataType/PackDataType.log @@ -1895,5 +1895,5 @@ design: (work@kmac_keymgr) ============================== Begin RoundTrip Results ============================== [roundtrip]: ${SURELOG_DIR}/tests/PackDataType/builtin.sv | ${SURELOG_DIR}/build/regression/PackDataType/roundtrip/builtin_000.sv | 0 | 0 | -[roundtrip]: ${SURELOG_DIR}/tests/PackDataType/dut.sv | ${SURELOG_DIR}/build/regression/PackDataType/roundtrip/dut_000.sv | 7 | 24 | +[roundtrip]: ${SURELOG_DIR}/tests/PackDataType/dut.sv | ${SURELOG_DIR}/build/regression/PackDataType/roundtrip/dut_000.sv | 8 | 24 | ============================== End RoundTrip Results ============================== diff --git a/tests/PackStructVar/PackStructVar.log b/tests/PackStructVar/PackStructVar.log index b9bd22f1e9..9d9c4a868d 100644 --- a/tests/PackStructVar/PackStructVar.log +++ b/tests/PackStructVar/PackStructVar.log @@ -2015,5 +2015,5 @@ design: (work@flash_ctrl) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/PackStructVar/dut.sv | ${SURELOG_DIR}/build/regression/PackStructVar/roundtrip/dut_000.sv | 7 | 47 | +[roundtrip]: ${SURELOG_DIR}/tests/PackStructVar/dut.sv | ${SURELOG_DIR}/build/regression/PackStructVar/roundtrip/dut_000.sv | 8 | 47 | ============================== End RoundTrip Results ============================== diff --git a/tests/ParamConstPush/ParamConstPush.log b/tests/ParamConstPush/ParamConstPush.log index 9eee8746e3..6ef93adba7 100644 --- a/tests/ParamConstPush/ParamConstPush.log +++ b/tests/ParamConstPush/ParamConstPush.log @@ -770,5 +770,5 @@ design: (work@top) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/ParamConstPush/dut.sv | ${SURELOG_DIR}/build/regression/ParamConstPush/roundtrip/dut_000.sv | 2 | 11 | +[roundtrip]: ${SURELOG_DIR}/tests/ParamConstPush/dut.sv | ${SURELOG_DIR}/build/regression/ParamConstPush/roundtrip/dut_000.sv | 3 | 11 | ============================== End RoundTrip Results ============================== diff --git a/tests/ParamOverload3/ParamOverload3.log b/tests/ParamOverload3/ParamOverload3.log index 538d1bc3a7..91c14c6cad 100644 --- a/tests/ParamOverload3/ParamOverload3.log +++ b/tests/ParamOverload3/ParamOverload3.log @@ -3649,5 +3649,5 @@ design: (work@top) ============================== End Linting Results ============================== ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/ParamOverload3/dut.sv | ${SURELOG_DIR}/build/regression/ParamOverload3/roundtrip/dut_000.sv | 23 | 64 | +[roundtrip]: ${SURELOG_DIR}/tests/ParamOverload3/dut.sv | ${SURELOG_DIR}/build/regression/ParamOverload3/roundtrip/dut_000.sv | 24 | 64 | ============================== End RoundTrip Results ============================== diff --git a/tests/ParamRef/ParamRef.log b/tests/ParamRef/ParamRef.log index 8849e10c78..0d2ec74c58 100644 --- a/tests/ParamRef/ParamRef.log +++ b/tests/ParamRef/ParamRef.log @@ -927,5 +927,5 @@ design: (work@top_earlgrey) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/ParamRef/dut.sv | ${SURELOG_DIR}/build/regression/ParamRef/roundtrip/dut_000.sv | 7 | 27 | +[roundtrip]: ${SURELOG_DIR}/tests/ParamRef/dut.sv | ${SURELOG_DIR}/build/regression/ParamRef/roundtrip/dut_000.sv | 8 | 27 | ============================== End RoundTrip Results ============================== diff --git a/tests/StructVar/StructVar.log b/tests/StructVar/StructVar.log index 33dd80ff48..27e61cf543 100644 --- a/tests/StructVar/StructVar.log +++ b/tests/StructVar/StructVar.log @@ -28,7 +28,7 @@ bit_typespec 5 constant 83 cont_assign 3 design 1 -enum_const 1 +enum_const 3 enum_typespec 1 gen_for 1 gen_scope 4 @@ -67,7 +67,7 @@ bit_typespec 5 constant 83 cont_assign 5 design 1 -enum_const 1 +enum_const 3 enum_typespec 1 gen_for 1 gen_scope 6 @@ -1916,6 +1916,8 @@ design: (work@test) \_operation: , line:62:4, endln:62:37 |vpiName:PMP_MODE_TOR |vpiFullName:work@test.u3.g_pmp_csrs[0].PMP_MODE_TOR + |vpiActual: + \_enum_const: (PMP_MODE_TOR) \_operation: , line:61:24, endln:62:38 |vpiParent: \_cont_assign: , line:61:10, endln:62:38 @@ -2003,6 +2005,8 @@ design: (work@test) \_operation: , line:62:4, endln:62:37 |vpiName:PMP_MODE_TOR |vpiFullName:work@test.u3.g_pmp_csrs[1].PMP_MODE_TOR + |vpiActual: + \_enum_const: (PMP_MODE_TOR) \_operation: , line:61:24, endln:62:38 |vpiParent: \_cont_assign: , line:61:10, endln:62:38 @@ -2087,6 +2091,13 @@ design: (work@test) |vpiGenScope: \_gen_scope: (work@test.u3.g_pmp_csrs[0]), line:59:33, endln:64:5 \_int_typespec: +\_enum_const: (PMP_MODE_TOR) + |vpiParent: + \_ref_obj: (work@test.u3.g_pmp_csrs[0].PMP_MODE_TOR), line:62:25, endln:62:37 + |vpiName:PMP_MODE_TOR + |BIN:01 + |vpiDecompile:2'b01 + |vpiSize:2 \_gen_scope: (work@test.u3.g_pmp_csrs[1]), line:59:33, endln:64:5 |vpiParent: \_gen_scope_array: (work@test.u3.g_pmp_csrs[1]), line:59:33, endln:64:5 @@ -2103,6 +2114,13 @@ design: (work@test) |vpiGenScope: \_gen_scope: (work@test.u3.g_pmp_csrs[1]), line:59:33, endln:64:5 \_int_typespec: +\_enum_const: (PMP_MODE_TOR) + |vpiParent: + \_ref_obj: (work@test.u3.g_pmp_csrs[1].PMP_MODE_TOR), line:62:25, endln:62:37 + |vpiName:PMP_MODE_TOR + |BIN:01 + |vpiDecompile:2'b01 + |vpiSize:2 \_int_typespec: =================== [ FATAL] : 0 diff --git a/third_party/tests/AzadiRTL/AzadiRTL.log b/third_party/tests/AzadiRTL/AzadiRTL.log index 6cb2ff3e0f..ced233a881 100644 --- a/third_party/tests/AzadiRTL/AzadiRTL.log +++ b/third_party/tests/AzadiRTL/AzadiRTL.log @@ -13827,7 +13827,7 @@ constant 274311 cont_assign 7035 delay_control 4 design 1 -enum_const 53131 +enum_const 53149 enum_typespec 16315 enum_var 156 event_control 383 @@ -13853,7 +13853,7 @@ int_var 272 integer_typespec 256 integer_var 20 io_decl 197 -logic_net 10750 +logic_net 10748 logic_typespec 63995 logic_var 4577 long_int_typespec 6 @@ -13908,7 +13908,7 @@ constant 275928 cont_assign 15432 delay_control 8 design 1 -enum_const 53136 +enum_const 53154 enum_typespec 16316 enum_var 184 event_control 1490 @@ -13934,7 +13934,7 @@ int_var 528 integer_typespec 256 integer_var 78 io_decl 485 -logic_net 10750 +logic_net 10748 logic_typespec 63995 logic_var 6546 long_int_typespec 6 diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log index 4378993f2f..609889ebfa 100644 --- a/third_party/tests/CoresSweRV/CoresSweRV.log +++ b/third_party/tests/CoresSweRV/CoresSweRV.log @@ -2434,7 +2434,7 @@ delay_control 54 design 1 disable_fork 5 do_while 51 -enum_const 503 +enum_const 1087 enum_typespec 94 enum_var 196 event_control 70 @@ -2540,7 +2540,7 @@ delay_control 170 design 1 disable_fork 15 do_while 146 -enum_const 663 +enum_const 1247 enum_typespec 165 enum_var 1653 event_control 132 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 2631215223..6baf190014 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -65,21 +65,21 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess [ 6%] Generating 10_lsu_bus_intf.sv -[ 12%] Generating 11_ifu_bp_ctl.sv -[ 18%] Generating 12_beh_lib.sv +[ 12%] Generating 12_beh_lib.sv +[ 18%] Generating 11_ifu_bp_ctl.sv [ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv -[ 50%] Generating 2_ahb_to_axi4.sv -[ 56%] Generating 1_lsu_stbuf.sv +[ 50%] Generating 1_lsu_stbuf.sv +[ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 8_ifu_aln_ctl.sv -[100%] Generating 9_tb_top.sv +[ 93%] Generating 9_tb_top.sv +[100%] Generating 8_ifu_aln_ctl.sv [100%] Built target Parse Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". @@ -2509,7 +2509,7 @@ delay_control 54 design 1 disable_fork 5 do_while 51 -enum_const 503 +enum_const 1087 enum_typespec 94 enum_var 196 event_control 70 @@ -2615,7 +2615,7 @@ delay_control 170 design 1 disable_fork 15 do_while 146 -enum_const 663 +enum_const 1247 enum_typespec 165 enum_var 1653 event_control 132 diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log index c8c9895386..4aa17d6243 100644 --- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log +++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log @@ -6172,7 +6172,7 @@ class_var 3 constant 344035 cont_assign 19794 design 1 -enum_const 2548 +enum_const 3632 enum_typespec 309 enum_var 404 event_control 721 @@ -6247,7 +6247,7 @@ class_var 3 constant 348743 cont_assign 47364 design 1 -enum_const 2553 +enum_const 3637 enum_typespec 310 enum_var 726 event_control 4855 diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log index 206b4a86d6..e206b4d428 100644 --- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log +++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log @@ -14345,7 +14345,7 @@ class_var 3 constant 926727 cont_assign 39267 design 1 -enum_const 31253 +enum_const 32514 enum_typespec 8348 enum_var 1174 event_control 1182 @@ -14373,7 +14373,7 @@ integer_var 8 interface_inst 10 interface_typespec 1 io_decl 433 -logic_net 68737 +logic_net 68734 logic_typespec 228832 logic_var 30672 method_func_call 1 @@ -14430,7 +14430,7 @@ class_var 3 constant 936086 cont_assign 147474 design 1 -enum_const 31258 +enum_const 32519 enum_typespec 8349 enum_var 1925 event_control 15153 @@ -14458,7 +14458,7 @@ integer_var 12 interface_inst 10 interface_typespec 1 io_decl 19631 -logic_net 68737 +logic_net 68734 logic_typespec 228832 logic_var 81286 method_func_call 1 diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log index a8ebeb92f7..7b9c638ecf 100644 --- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log +++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log @@ -5827,7 +5827,7 @@ class_var 3 constant 321233 cont_assign 19205 design 1 -enum_const 2446 +enum_const 3532 enum_typespec 258 enum_var 342 event_control 746 @@ -5908,7 +5908,7 @@ class_var 3 constant 325987 cont_assign 43470 design 1 -enum_const 2451 +enum_const 3537 enum_typespec 259 enum_var 520 event_control 4876 diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log index 63351a9b25..ec621797ce 100644 --- a/third_party/tests/Ibex/Ibex.log +++ b/third_party/tests/Ibex/Ibex.log @@ -809,7 +809,7 @@ design 1 disable 10 disable_fork 29 do_while 191 -enum_const 18934 +enum_const 18938 enum_typespec 3282 enum_var 1137 event_control 174 diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log index de9629d9f1..5bd2e2af5d 100644 --- a/third_party/tests/IncompTitan/IncompTitan.log +++ b/third_party/tests/IncompTitan/IncompTitan.log @@ -5340,7 +5340,7 @@ constant 403123 cont_assign 18019 cover 20 design 1 -enum_const 5649 +enum_const 5870 enum_typespec 1474 enum_var 133 event_control 223 diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index b3de0063d2..e08fe09ecf 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -896,7 +896,7 @@ class_var 3 constant 141204 cont_assign 2227 design 1 -enum_const 13241 +enum_const 13261 enum_typespec 1302 enum_var 38 event_control 277 @@ -976,7 +976,7 @@ class_var 3 constant 143226 cont_assign 5561 design 1 -enum_const 13246 +enum_const 13266 enum_typespec 1303 enum_var 58 event_control 910 diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log index af0ebb9d55..a0b225783b 100644 --- a/third_party/tests/Opentitan/Earlgrey.log +++ b/third_party/tests/Opentitan/Earlgrey.log @@ -25178,7 +25178,7 @@ class_var 3 constant 213980 cont_assign 13781 design 1 -enum_const 2016 +enum_const 2037 enum_typespec 206 enum_var 280 event_control 590 @@ -25251,7 +25251,7 @@ class_var 3 constant 217424 cont_assign 30746 design 1 -enum_const 2021 +enum_const 2042 enum_typespec 207 enum_var 432 event_control 3782 diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index af910a861b..cb340f7b56 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -4199,7 +4199,7 @@ delay_control 53 design 1 disable_fork 5 do_while 51 -enum_const 2392 +enum_const 2413 enum_typespec 281 enum_var 461 event_control 609 @@ -4316,7 +4316,7 @@ delay_control 168 design 1 disable_fork 15 do_while 146 -enum_const 2552 +enum_const 2573 enum_typespec 352 enum_var 2070 event_control 3864 From 72862c0ee4c581df276fbf3d47fcb5405baa8018 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Wed, 2 Oct 2024 20:49:03 -0700 Subject: [PATCH 2/3] import package item fix for synlig --- .vscode/launch.json | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 3f13a84951..9797618053 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -908,25 +908,6 @@ } ] }, - { - "name": "kmac", - "type": "cppdbg", - "request": "launch", - "program": "${workspaceFolder}/dbuild/bin/surelog", - "args": ["-parse", "sha3_pkg.sv", "kmac_core.sv", "kmac.sv", "-top", "kmac", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-elabuhdm", "-nobuiltin"], - "stopAtEntry": false, - "cwd": "/home/alain/os-fpga/Raptor/tests/Testcases/kmac", - "environment": [], - "externalConsole": false, - "MIMode": "gdb", - "setupCommands": [ - { - "description": "Enable pretty-printing for gdb", - "text": "-enable-pretty-printing", - "ignoreFailures": true - } - ] - }, { "name": "ScratchPad_v", "type": "cppdbg", From 6a4fa76854fb1ee9eaa33aa01611b036262e6dad Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Wed, 2 Oct 2024 20:49:19 -0700 Subject: [PATCH 3/3] import package item fix for synlig --- tests/Kmac/Kmac.log | 3333 +++++++++++++++++++++++++++++++++++++++ tests/Kmac/Kmac.sl | 2 + tests/Kmac/kmac.sv | 16 + tests/Kmac/kmac_core.sv | 36 + tests/Kmac/sha3_pkg.sv | 32 + 5 files changed, 3419 insertions(+) create mode 100644 tests/Kmac/Kmac.log create mode 100644 tests/Kmac/Kmac.sl create mode 100644 tests/Kmac/kmac.sv create mode 100644 tests/Kmac/kmac_core.sv create mode 100644 tests/Kmac/sha3_pkg.sv diff --git a/tests/Kmac/Kmac.log b/tests/Kmac/Kmac.log new file mode 100644 index 0000000000..1edefee1f9 --- /dev/null +++ b/tests/Kmac/Kmac.log @@ -0,0 +1,3333 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/Kmac/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work 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el<23:54> +n<> u<164> t p<369> c<163> s<367> l<23:2> el<23:54> +n<> u<165> t p<364> s<363> l<24:5> el<24:16> +n<> u<166> t p<167> l<25:5> el<25:11> +n<> u<167> t p<356> c<166> s<169> l<25:5> el<25:11> +n<> u<168> t p<169> l<25:12> el<25:16> +n<> u<169> t p<356> c<168> s<173> l<25:12> el<25:16> +n u<170> t p<171> l<25:18> el<25:28> +n<> u<171> t p<172> c<170> l<25:18> el<25:28> +n<> u<172> t p<173> c<171> l<25:18> el<25:28> +n<> u<173> t p<356> c<172> s<206> l<25:18> el<25:28> +n u<174> t p<175> l<26:7> el<26:11> +n<> u<175> t p<176> c<174> l<26:7> el<26:11> +n<> u<176> t p<177> c<175> l<26:7> el<26:11> +n<> u<177> t p<206> c<176> s<205> l<26:7> el<26:11> +n u<178> t p<179> l<26:13> el<26:29> +n<> u<179> t p<182> c<178> s<181> l<26:13> el<26:29> +n<> u<180> t p<181> l<26:30> el<26:30> +n<> u<181> t p<195> c<193> l<26:56> el<26:62> +n<> u<195> t p<196> c<188> l<26:46> el<26:62> +n<> u<196> t p<197> c<195> l<26:46> el<26:62> +n<> u<197> t p<198> c<196> l<26:46> el<26:62> +n<> u<198> t p<199> c<187> l<26:32> el<26:63> +n<> u<199> t p<200> c<198> l<26:32> el<26:63> +n<> u<200> t p<201> c<199> l<26:32> el<26:63> +n<> u<201> t p<202> c<182> l<26:13> el<26:63> +n<> u<202> t p<203> c<201> l<26:13> el<26:63> +n<> u<203> t p<204> c<202> l<26:13> el<26:64> +n<> u<204> t p<205> c<203> l<26:13> el<26:64> +n<> u<205> t p<206> c<204> l<26:13> el<26:64> +n<> u<206> t p<356> c<177> s<239> l<26:7> el<26:64> +n u<207> t p<208> l<27:7> el<27:11> +n<> u<208> t p<209> c<207> l<27:7> el<27:11> +n<> u<209> t p<210> c<208> l<27:7> el<27:11> +n<> u<210> t p<239> c<209> s<238> l<27:7> el<27:11> +n u<211> t p<212> l<27:13> el<27:29> +n<> u<212> t p<215> c<211> s<214> l<27:13> el<27:29> +n<> u<213> t p<214> l<27:30> el<27:30> +n<> u<214> t p<228> c<226> l<27:56> el<27:62> +n<> u<228> t p<229> c<221> l<27:46> el<27:62> +n<> u<229> t p<230> c<228> l<27:46> el<27:62> +n<> u<230> t p<231> c<229> l<27:46> el<27:62> +n<> u<231> t p<232> c<220> l<27:32> el<27:63> +n<> u<232> t p<233> c<231> l<27:32> el<27:63> +n<> u<233> t p<234> c<232> l<27:32> el<27:63> +n<> u<234> t p<235> c<215> l<27:13> el<27:63> +n<> u<235> t p<236> c<234> l<27:13> el<27:63> +n<> u<236> t p<237> c<235> l<27:13> el<27:64> +n<> u<237> t p<238> c<236> l<27:13> el<27:64> +n<> u<238> t p<239> c<237> l<27:13> el<27:64> +n<> u<239> t p<356> c<210> s<272> l<27:7> el<27:64> +n u<240> t p<241> l<28:7> el<28:11> +n<> u<241> t p<242> c<240> l<28:7> el<28:11> +n<> u<242> t p<243> c<241> l<28:7> el<28:11> +n<> u<243> t p<272> c<242> s<271> l<28:7> el<28:11> +n u<244> t p<245> l<28:13> el<28:29> +n<> u<245> t p<248> c<244> s<247> l<28:13> el<28:29> +n<> u<246> t p<247> l<28:30> el<28:30> +n<> u<247> t p<261> c<259> l<28:56> el<28:62> +n<> u<261> t p<262> c<254> l<28:46> el<28:62> +n<> u<262> t p<263> c<261> l<28:46> el<28:62> +n<> u<263> t p<264> c<262> l<28:46> el<28:62> +n<> u<264> t p<265> c<253> l<28:32> el<28:63> +n<> u<265> t p<266> c<264> l<28:32> el<28:63> +n<> u<266> t p<267> c<265> l<28:32> el<28:63> +n<> u<267> t p<268> c<248> l<28:13> el<28:63> +n<> u<268> t p<269> c<267> l<28:13> el<28:63> +n<> u<269> t p<270> c<268> l<28:13> el<28:64> +n<> u<270> t p<271> c<269> l<28:13> el<28:64> +n<> u<271> t p<272> c<270> l<28:13> el<28:64> +n<> u<272> t p<356> c<243> s<305> l<28:7> el<28:64> +n u<273> t p<274> l<29:7> el<29:11> +n<> u<274> t p<275> c<273> l<29:7> el<29:11> +n<> u<275> t p<276> c<274> l<29:7> el<29:11> +n<> u<276> t p<305> c<275> s<304> l<29:7> el<29:11> +n u<277> t p<278> l<29:13> el<29:29> +n<> u<278> t p<281> c<277> s<280> l<29:13> el<29:29> +n<> u<279> t p<280> l<29:30> el<29:30> +n<> u<280> t p<294> c<292> l<29:56> el<29:62> +n<> u<294> t p<295> c<287> l<29:46> el<29:62> +n<> u<295> t p<296> c<294> l<29:46> el<29:62> +n<> u<296> t p<297> c<295> l<29:46> el<29:62> +n<> u<297> t p<298> c<286> l<29:32> el<29:63> +n<> u<298> t p<299> c<297> l<29:32> el<29:63> +n<> u<299> t p<300> c<298> l<29:32> el<29:63> +n<> u<300> t p<301> c<281> l<29:13> el<29:63> +n<> u<301> t p<302> c<300> l<29:13> el<29:63> +n<> u<302> t p<303> c<301> l<29:13> el<29:64> +n<> u<303> t p<304> c<302> l<29:13> el<29:64> +n<> u<304> t p<305> c<303> l<29:13> el<29:64> +n<> u<305> t p<356> c<276> s<338> l<29:7> el<29:64> +n u<306> t p<307> l<30:7> el<30:11> +n<> u<307> t p<308> c<306> l<30:7> el<30:11> +n<> u<308> t p<309> c<307> l<30:7> el<30:11> +n<> u<309> t p<338> c<308> s<337> l<30:7> el<30:11> +n u<310> t p<311> l<30:13> el<30:29> +n<> u<311> t p<314> c<310> s<313> l<30:13> el<30:29> +n<> u<312> t p<313> l<30:30> el<30:30> +n<> u<313> t p<327> c<325> l<30:56> el<30:62> +n<> u<327> t p<328> c<320> l<30:46> el<30:62> +n<> u<328> t p<329> c<327> l<30:46> el<30:62> +n<> u<329> t p<330> c<328> l<30:46> el<30:62> +n<> u<330> t p<331> c<319> l<30:32> el<30:63> +n<> u<331> t p<332> c<330> l<30:32> el<30:63> +n<> u<332> t p<333> c<331> l<30:32> el<30:63> +n<> u<333> t p<334> c<314> l<30:13> el<30:63> +n<> u<334> t p<335> c<333> l<30:13> el<30:63> +n<> u<335> t p<336> c<334> l<30:13> el<30:64> +n<> u<336> t p<337> c<335> l<30:13> el<30:64> +n<> u<337> t p<338> c<336> l<30:13> el<30:64> +n<> u<338> t p<356> c<309> s<354> l<30:7> el<30:64> +n u<339> t p<340> l<32:16> el<32:32> +n<> u<340> t p<343> c<339> s<342> l<32:16> el<32:32> +n<> u<341> t p<342> l<32:33> el<32:33> +n<> u<342> t