-
Notifications
You must be signed in to change notification settings - Fork 0
/
netlist.pegjs
181 lines (133 loc) · 5.12 KB
/
netlist.pegjs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
{
const util = require('util');
const {astDirToDir} = options;
var chip;
var page;
var wires = {};
var nets = {};
var bpPins = {};
function AST(nodeType, props) {
const loc = location();
// So we can toString() and util.inspect() our location() values with readable results.
loc.__proto__.toString = loc[util.inspect.custom] = function() {
const [s, e] = [this.start ? this.start : this, this.end? this.end: this];
return `@${s.line}:${s.column}:${s.offset}..${e.line}:${e.column}:${e.offset}`;
};
return {
nodeType,
location: loc,
...props,
};
}
function addNet(page, chip, pin, dir, bpPin, net) {
const netAST = net.list;
net = net.text;
if (!nets[net]) nets[net] = [];
const n = {net, bpPin, netAST, page, chip, pin, dir: astDirToDir(dir)};
const key = `${chip.name}.${astDirToDir(dir)}.${pin}`;
wires[key] = n;
nets[net].push(n);
if (bpPin) {
if (!bpPins[bpPin]) bpPins[bpPin] = {};
bpPins[bpPin][key] = n;
}
}
}
compileable = blankLines? c:(stubBoard / backplane+ / board) { return c }
backplane = 'Backplane' _ ':' _
macros:( '{' _ m:macroDef* '}' _ {return m} )?
name:simpleID _ EOL
slots:slotDef+
{ return AST('Backplane', {name, macros, slots}); }
slotDef = blankLines? 'Slot' _ n:simpleID _ ':' _
module:module blankLines slotWires:wireDef* blankLines?
{ return AST('Slot', {n, module, slotWires, bpPins: {}}); }
module = macros:( '{' _ m:macroDef* '}' {return m} )? _
id:simpleID _ comments:$( !EOL . )*
{ return AST('ModuleID', {macros, id, comments}); }
macroDef = id:simpleID _ '=' _ value:$(number / simpleID) _
{ return AST('MacroDef', {id, value}); }
wireDef = _ slotPin:bpPinID _ farPin:bpPinID '[' slot:number ']' _ name:id _ blankLines
{ return AST('Wire', {slotPin, farPin, slot, name}); }
stubBoard = 'STUB IMPLEMENTATION' EOL p:pageDef*
{ return AST('Stub', {pages: p}); }
board = verilog:verilogDef? pages:(page / warning)+
{ const m = AST('Board', {pages, nets, wires, bpPins,
verilog: verilog && verilog.v[0] || undefined});
// Cleanly reinitialize accumulators for next board.
wires = {};
nets = {};
bpPins = {};
return m; }
page = p:pageDef n:chipDef*
{ p.chips = n; return p; }
pageDef = 'Page' _ ':' _ name:$( [^\r\n, ]+ ) _ ',' _ pdfRef:$( ( !EOL . )+ ) blankLines
{ page = {name, pdfRef};
return AST('Page', {name, pdfRef, chips: []}); }
warning = '%warning' _ s:$( !EOL . )* blankLines
{ console.error(`= = = = WARNING: ${s}`);
return AST('Page', {name: '%warning', pdfRef: 'none', chips: [], s}); }
verilogDef = '%verilog' _ EOL
v:verilogLines+
'%endverilog' _ EOL blankLines
{ return AST('Verilog', {v}); }
verilogLines = (!'%endverilog' (!EOL .)* EOL)+
{ return text(); }
chipDef = verilogDef
/ h:chipHead p:pinDef+
{ h.pins = p; return h; }
chipHead = !'Page' !'%verilog' !'%warning'
name:$idChunk ':' _ type:$([^ \t]+) _ desc:$( (!EOL . )+ ) blankLines
{ chip = {name, type, desc};
return AST('Chip', chip); }
pinDef = [ \t]+ pin:number _ dir:direction _ bpPin:bpPin? _ net:net blankLines
{ addNet(page, chip, pin, dir, bpPin, net);
return AST('Pin', {pin, dir, bpPin: bpPin ? bpPin.trim() : null, net}); }
direction = $('~>' / '~<')
bpPin = '{' pinID:bpPinID '}'
{ return pinID; }
bpPinID = $( [abcdef] [abcdefhjklmnprstuv] [12] )
// ONLY the `head:expr` is to be expanded. If there are `macroRef`
// instances inside the `selectorList`, those will have their own
// `head:expr` within them. Otherwise, the `idChunk` instances in the
// `selectorList` are symbols with no expansion.
macroRef = '[' head:expr list:( ',' id:idList {return id} )* ']'
{ return AST(list.length > 0 ? 'Selector' : 'Macro', {head, list}); }
idList = list:( macroRef / idChunk )*
{ return AST('IDList', {list}); }
NC = '%NC%' { return AST('IDChunk', {name: '%NC%'}); }
idChunk = NC
/ name:$[-/#%.+& <>()a-z0-9=]+
{ return AST('IDChunk', {name}); }
// like idChunk but allows ',' in the identifier in non-macro context
id = NC
/ name:[-/#%,.+*& <>()a-z0-9=^]+
{ return AST('IDChunk', {name: text().replace(/\\[\n\r]\s*/g, '')}); }
expr = sum
sum = l:product _ op:$[-+] _ r:sum
{ return AST(op, {l, r}); }
/ product
product = l:primary _ op:$[*/] _ r:product
{ return AST(op, {l, r}); }
/ primary
primary = value:$number
{ return AST('Value', {value}); }
/ '(' _ val:sum _ ')'
{ return val; }
/ macroName
number = $[0-9]+
macroName = name:simpleID
{ return AST('IDChunk', {name}); }
simpleID = $[a-zA-Z0-9]+
net = '%NC%' { return AST('NoConnect', {text: text(), value: text()}); }
/ [01] { return AST('Value', {value: parseInt(text(), 2), text: text()}); }
/ '`' (!EOL .)+
{ return AST('IDList', {list: [AST('VerilogChunk', {name: text()})]}); }
/ list:( macroRef / idWith_ )+
{ return AST('IDList', {list, text: text()}); }
idWith_ = ( '\\' EOL _ )* id:id
{ return id; }
EOL "end of line" = '\r\n' / '\r' / '\n'
blankLines = (_ EOL)+
_ "whitespace or comments"
= ( [ \t]+ / '\\' EOL / '//' ( !EOL . )* / '/*' ( !'*/' . )* '*/' )*