wb_async_reg: stb master unasserted pulse not registering

[rdolbeau]

Hello,

After working some more with wb_async_reg, I think I found a bug under some (extreme) circumstances.
If the master's clock is significantly faster than the slave's, then it's possible for the slave to miss the master's STB unasserted pulse, leading to a failure to recognize the next transaction.

At the end of a transaction, the slave will see the ack and properly unassert STB on its side, and properly tell the master that will eventually unassert STB on its side. However, if the master starts a new cycle quickly enough (re-asserting STB), the wbs_stb_sync1 register set from wbm_stb_i_reg using the slave clock might completely miss the unasserted STB from the master. The slave will therefore never see a rising edge on STB (wbs_cyc_o_sync2 is never unasserted), and the bus will hang.