{"payload":{"header_redesign_enabled":false,"results":[{"id":"228525485","archived":false,"color":"#adb2cb","followers":15,"has_funding_file":false,"hl_name":"alvarezpj/single-cycle-cpu","hl_trunc_description":"VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":228525485,"name":"single-cycle-cpu","owner_id":19765128,"owner_login":"alvarezpj","updated_at":"2019-12-17T03:32:05.085Z","has_issues":true}},"sponsorable":false,"topics":["fpga","vhdl","quartus","single-cycle","de2-board","altera-fpga"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aalvarezpj%252Fsingle-cycle-cpu%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/alvarezpj/single-cycle-cpu/star":{"post":"XS_7LMwMC20XNilR2rmwvCuehjh7GgDL6nqevpVEty-jd6xIsrwQUzO04rnrmGi0dnaYwIkyCZA7ThXmkzBvYA"},"/alvarezpj/single-cycle-cpu/unstar":{"post":"baNgspZeXW5Odti9_zDDzGUv494xiGV5Mb0yxeBBVEzby3U6LtKqBkjtk3V-SvXxD2-6Hc96WktZk9RDeY7B5Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"wJRFvJ7nAsMY2Zf1OG0RVDMmidwqGvls4E-NJ7-8caA_z-UvIVtPA3ttEhpTPspRReJt_1K9giwX4X1hSUUwFA"}}},"title":"Repository search results"}