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ad4858_fmcz #1098
ad4858_fmcz #1098
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Looks good to me now
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library/axi_ad4858/axi_ad4858_ip.tcl
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set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc] | ||
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# UNCOMENT when entering hdl repo |
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Shouldn't this comment be removed?
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Yes
projects/ad4858_fmcz/Readme.md
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Can you please also add the make parameters that could be used?
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Done
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Looks good to me! Both CMOS and LVDS modes were built without errors or critical warnings.
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Looks good. The library/Makefile
file would need an update to latest master-based version.
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I squashed the latest commits from requests and fixed the conflict in the library/Makefile. The Makefile had an addition of another IP in the main branch. |
The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC. Features: - AXI based configuration - LVDS and CMOS support - Configurable number of active data lines (CMOS - build-time configurable) - Oversampling support - Supports packet formats 0,1,2 or 3 - CRC check support - Real-time data header access - Channel based raw data access(0x0408) - Xilinx devices compatible Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
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V2:
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Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with buffered differential, wide common range picoamp inputs. The design supports: - CMOS and LVDS interfaces(at build time) - Runtime sampling changes - Store captured samples in RAM, through DMA (available via software support) Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
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Initial design.
Tested in hardware.