From cd9e926b3df83ac294583a3578975d7be352a764 Mon Sep 17 00:00:00 2001 From: Tahsin Mutlugun Date: Thu, 12 Dec 2024 17:03:03 -0600 Subject: [PATCH 1/2] Fix MAX32657 SPI pin initialization Use correct pin numbers when initializing SPI on MAX32657. Signed-off-by: Tahsin Mutlugun --- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index ac48b4f2b2..418dce7321 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -88,30 +88,20 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS //clear mask gpio_cfg_spi.mask = 0; - // TODO(ME30): Validate pin assignments - // check rest of the pins if (pins.clock) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; + gpio_cfg_spi.mask |= MXC_GPIO_PIN_6; } if (pins.miso) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; + gpio_cfg_spi.mask |= MXC_GPIO_PIN_4; } if (pins.mosi) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; - } - - if (pins.sdio2) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; - } - - if (pins.sdio3) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; + gpio_cfg_spi.mask |= MXC_GPIO_PIN_2; } if (pins.ss0) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; + gpio_cfg_spi.mask |= MXC_GPIO_PIN_3; } gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; From 80f678c29b3afe8a1b94153227689a3689a3cf52 Mon Sep 17 00:00:00 2001 From: Tahsin Mutlugun Date: Thu, 12 Dec 2024 17:04:10 -0600 Subject: [PATCH 2/2] Return correct peripheral clock rate for MAX32657 SPI MAX32657 SPI input clock rate should be APB clock divided by two. Signed-off-by: Tahsin Mutlugun --- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 35 ++----------------- 1 file changed, 2 insertions(+), 33 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index 418dce7321..1b97472b0c 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -136,40 +136,9 @@ int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) { - int retval; - - // TODO(ME30): Validate this logic - int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> - MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; - switch (sys_clk) { - case MXC_SYS_CLOCK_IPO: - retval = IPO_FREQ; - break; - case MXC_SYS_CLOCK_IBRO: - retval = IBRO_FREQ; - break; - case MXC_SYS_CLOCK_INRO: - retval = INRO_FREQ; - break; - case MXC_SYS_CLOCK_ERTCO: - retval = ERTCO_FREQ; - break; - // TODO(ME30): EXTCLK definition is missing from registers - // case MXC_SYS_CLOCK_EXTCLK: - // retval = EXTCLK_FREQ; - // break; -#if TARGET_NUM == 32655 || TARGET_NUM == 32680 - case MXC_SYS_CLOCK_ERFO: - retval = ERFO_FREQ; - break; -#endif - default: - return E_BAD_STATE; - } - - retval /= 2; + (void)spi; - return retval; + return PeripheralClock / 2; } int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz)