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vmir_jit_arm.c
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vmir_jit_arm.c
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/*
* Copyright (c) 2016 Lonelycoder AB
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#define ARM_COND_EQ 0x00000000
#define ARM_COND_NE 0x10000000
#define ARM_COND_UGT 0x80000000
#define ARM_COND_UGE 0x20000000
#define ARM_COND_ULT 0x30000000
#define ARM_COND_ULE 0x90000000
#define ARM_COND_SGT 0xc0000000
#define ARM_COND_SGE 0xa0000000
#define ARM_COND_SLT 0xb0000000
#define ARM_COND_SLE 0xd0000000
#define ARM_COND_AL 0xe0000000
#define VMIR_VM_JIT
/**
* Convert LLVM pred to ARM cond
*/
static uint32_t
armcond(int pred)
{
uint32_t cond;
switch(pred) {
case ICMP_EQ: cond = ARM_COND_EQ; break;
case ICMP_NE: cond = ARM_COND_NE; break;
case ICMP_UGT: cond = ARM_COND_UGT; break;
case ICMP_UGE: cond = ARM_COND_UGE; break;
case ICMP_ULT: cond = ARM_COND_ULT; break;
case ICMP_ULE: cond = ARM_COND_ULE; break;
case ICMP_SGT: cond = ARM_COND_SGT; break;
case ICMP_SGE: cond = ARM_COND_SGE; break;
case ICMP_SLT: cond = ARM_COND_SLT; break;
case ICMP_SLE: cond = ARM_COND_SLE; break;
default:
abort();
}
return cond;
}
static int
arm_machinereg(int reg)
{
if(reg < 5)
return reg + 4; // r4, r5, r6, r7, r8
return reg + 5; // r10, r11
}
#define JIT_MACHINE_REGS 7
/**
* Registers
*
* r0 - return value pointer
* r1 - Register frame
* r2 - Stack frame, also used as TMP-C
* r3 - Memory
* r4 - r8 "machine registers"
* r9 - TMP-B
* r10 - r11 "machine registers"
* r14 - Link register, used for TMP-A
*/
#define REG_SAVE_MASK 0x4ff0
#define REG_RESTORE_MASK 0x8ff0
/**
* Registers
*/
#define R_RET 0
#define R_VMSTACK 1
#define R_TMPC 2
#define R_MEM 3
#define R_TMPB 9
#define R_TMPA 14
#define R_PC 15
#define LITERAL_POOL_MAX_SIZE 256
#define LITERAL_POOL_CONSTANT 0
#define LITERAL_POOL_VMBB 1
typedef struct jitctx {
int literal_pool_use;
struct {
uint32_t value;
uint32_t instr;
int type;
} literal_pool[LITERAL_POOL_MAX_SIZE];
} jitctx_t;
static int rotr32(uint32_t v, uint32_t bits)
{
return (v >> bits) | (v << (32 - bits));
}
/**
*
*/
static int
rotl32(uint32_t v, uint32_t bits)
{
return (v << bits) | (v >> (32 - bits));
}
/**
*
*/
static int
make_imm12(uint32_t v)
{
if((v & 0xffffff00) == 0)
return v;
int rot = __builtin_ctz(v) & ~1;
uint32_t v2 = rotr32(v, rot);
if((v2 & 0xffffff00) == 0) {
rot = 32 - rot;
return rotl32(v, rot) | (rot << 7);
}
return -1;
}
/**
*
*/
static void
jit_push(ir_unit_t *iu, uint32_t opcode)
{
if(iu->iu_jit_ptr + 4 >= iu->iu_jit_mem_alloced) {
assert(iu->iu_jit_mem == NULL); // TODO, realloc when we run out of space
iu->iu_jit_mem_alloced = 1024 * 1024 * 16;
iu->iu_jit_mem = mmap(NULL, iu->iu_jit_mem_alloced,
PROT_EXEC | PROT_READ | PROT_WRITE,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
}
uint32_t *p = iu->iu_jit_mem + iu->iu_jit_ptr;
*p = opcode;
iu->iu_jit_ptr += 4;
}
/**
*
*/
static void
jit_pushal(ir_unit_t *iu, uint32_t opcode)
{
jit_push(iu, opcode | ARM_COND_AL);
}
/**
*
*/
static void
jit_push_literal_pool(ir_unit_t *iu, jitctx_t *jc)
{
for(int i = 0; i < jc->literal_pool_use; i++) {
int imm12 = iu->iu_jit_ptr - jc->literal_pool[i].instr - 8;
assert(imm12 < 4096);
uint32_t *p = iu->iu_jit_mem + jc->literal_pool[i].instr;
switch(jc->literal_pool[i].type) {
case LITERAL_POOL_VMBB:
VECTOR_PUSH_BACK(&iu->iu_jit_vmbb_fixups, iu->iu_jit_ptr);
break;
}
*p |= imm12;
jit_push(iu, jc->literal_pool[i].value);
}
jc->literal_pool_use = 0;
}
/**
*
*/
static void
jit_loadimm_from_literal_pool_cond(ir_unit_t *iu, uint32_t imm, int Rd,
int type, jitctx_t *jc,
uint32_t cond)
{
assert(jc->literal_pool_use != LITERAL_POOL_MAX_SIZE);
jc->literal_pool[jc->literal_pool_use].value = imm;
jc->literal_pool[jc->literal_pool_use].instr = iu->iu_jit_ptr;
jc->literal_pool[jc->literal_pool_use].type = type;
jc->literal_pool_use++;
jit_push(iu, cond | (1 << 26) | (1 << 24) | (1 << 23) | (0x1f << 16) |
(Rd << 12));
}
static void
jit_loadimm_from_literal_pool(ir_unit_t *iu, uint32_t imm, int Rd,
int type, jitctx_t *jc)
{
jit_loadimm_from_literal_pool_cond(iu, imm, Rd, type, jc,
ARM_COND_AL);
}
/**
*
*/
static void
jit_loadimm_cond(ir_unit_t *iu, uint32_t imm, int Rd, jitctx_t *jc, uint32_t cond)
{
int imm12 = make_imm12(imm);
if(imm12 != -1) {
// MOV A1 encoding
jit_push(iu, cond | (1 << 25) | (1 << 24) | (1 << 23) | (1 << 21) |
(Rd << 12) | imm12);
return;
}
imm12 = make_imm12(~imm);
if(imm12 != -1) {
// MVN A1 encoding
jit_push(iu, cond |
(1 << 25) | (1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |
(Rd << 12) | imm12);
return;
}
// MOV A2 encoding ...
// ... is only available on ARMv7 so play it safe and only emit it
// if IDIV is available. Not sure if there is a better way to detect
if((uint32_t)imm <= 0xffff && iu->iu_jit_cpuflags & (1 << 17)) {
jit_push(iu, cond | (1 << 25) | (1 << 24) |
((imm & 0xf000) << 4) | (Rd << 12) | (imm & 0xfff));
return;
}
jit_loadimm_from_literal_pool_cond(iu, imm, Rd, 0, jc, cond);
}
/**
*
*/
static void
jit_loadimm(ir_unit_t *iu, uint32_t imm, int Rd, jitctx_t *jc)
{
return jit_loadimm_cond(iu, imm, Rd, jc, ARM_COND_AL);
}
/**
*
*/
static void
jit_push_add_imm(ir_unit_t *iu, int Rd, int Rn, int imm, int tmpreg,
jitctx_t *jc)
{
int imm12 = make_imm12(imm);
if(imm12 != -1) {
jit_pushal(iu, (1 << 25) | (1 << 23) | (Rn << 16) | (Rd << 12) | imm12);
} else {
jit_loadimm(iu, imm, tmpreg, jc);
jit_pushal(iu, (1 << 23) | (Rn << 16) | (Rd << 12) | tmpreg);
}
}
/**
*
*/
static uint32_t
jit_offset_to_imm12_U(int off)
{
assert(off < 4096 && off > -4096);
return off < 0 ? -off : off | (1 << 23);
}
static int
jit_offset_to_imm8_U(int offset)
{
if(offset < 256 && offset > -256) {
uint32_t U = 1 << 23;
if(offset < 0) {
offset = -offset;
U = 0;
}
return (offset & 0xf) | ((offset & 0xf0) << 4) | U;
}
return -1;
}
/**
* Load a value into a register
*
* If the value is a constant or stored on the regframe the register
* passed in 'reg' is used as a temoprary
*
* If the value is stored in a machine register, that register is returned
*/
#define JIT_LOAD_EXT_NONE 0
#define JIT_LOAD_EXT_UNSIGNED 1
#define JIT_LOAD_EXT_SIGNED 2
static int __attribute__((warn_unused_result))
jit_loadvalue_cond(ir_unit_t *iu, ir_valuetype_t vt, int reg, jitctx_t *jc,
uint32_t cond, int ext)
{
const ir_value_t *iv = value_get(iu, vt.value);
const ir_type_t *it = type_get(iu, vt.type);
int mr;
int imm8;
switch(iv->iv_class) {
case IR_VC_MACHINEREG:
mr = arm_machinereg(iv->iv_reg);
switch(legalize_type(it)) {
case IR_TYPE_INT8:
if(ext == JIT_LOAD_EXT_SIGNED) {
// SXTB
jit_push(iu, cond | (1 << 26) | (1 << 25) |
(1 << 23) | (1 << 21) | 0xf0070 |
(reg << 12) | mr);
return reg;
}
if(ext == JIT_LOAD_EXT_UNSIGNED) {
// UXTB
jit_push(iu, cond | (1 << 26) | (1 << 25) |
(1 << 23) | (1 << 22) | (1 << 21) | 0xf0070 |
(reg << 12) | mr);
return reg;
}
break;
case IR_TYPE_INT16:
if(ext == JIT_LOAD_EXT_SIGNED) {
// SXTH
jit_push(iu, cond | (1 << 26) | (1 << 25) |
(1 << 23) | (1 << 21) | (1 << 20) | 0xf0070 |
(reg << 12) | mr);
return reg;
}
if(ext == JIT_LOAD_EXT_UNSIGNED) {
// UXTH
jit_push(iu, cond | (1 << 26) | (1 << 25) |
(1 << 23) | (1 << 22) | (1 << 21) | (1 << 20) | 0xf0070 |
(reg << 12) | mr);
return reg;
}
break;
case IR_TYPE_INT1:
case IR_TYPE_INT32:
case IR_TYPE_FLOAT:
case IR_TYPE_POINTER:
break;
}
return mr;
case IR_VC_REGFRAME:
switch(legalize_type(it)) {
case IR_TYPE_INT8:
if(ext == JIT_LOAD_EXT_UNSIGNED) {
// LDRB
jit_push(iu, cond | (1 << 26) | (1 << 24) | (1 << 22) | (1 << 20) |
(R_VMSTACK << 16) | (reg << 12) |
jit_offset_to_imm12_U(iv->iv_reg));
break;
}
if(ext == JIT_LOAD_EXT_SIGNED) {
imm8 = jit_offset_to_imm8_U(iv->iv_reg);
if(imm8 != -1) {
// LDRSB
jit_push(iu, cond | (1 << 24) | (1 << 22) | (1 << 20) |
(R_VMSTACK << 16) | (reg << 12) | imm8 | 0xd0);
break;
}
printf("JIT_LOAD_EXT_SIGNED i8 from regframe not supported\n");
abort();
}
goto load32;
case IR_TYPE_INT16:
if(ext == JIT_LOAD_EXT_UNSIGNED) {
imm8 = jit_offset_to_imm8_U(iv->iv_reg);
if(imm8 != -1) {
// LDRH
jit_push(iu, cond | (1 << 24) | (1 << 22) | (1 << 20) |
(R_VMSTACK << 16) | (reg << 12) | imm8 | 0xb0);
break;
}
printf("JIT_LOAD_EXT_UNSIGNED i16 from regframe not supported\n");
abort();
}
if(ext == JIT_LOAD_EXT_SIGNED) {
imm8 = jit_offset_to_imm8_U(iv->iv_reg);
if(imm8 != -1) {
// LDRSH
jit_push(iu, cond | (1 << 24) | (1 << 22) | (1 << 20) |
(R_VMSTACK << 16) | (reg << 12) | imm8 | 0xf0);
break;
}
printf("JIT_LOAD_EXT_SIGNED i16 from regframe not supported\n");
abort();
}
goto load32;
case IR_TYPE_INT1:
case IR_TYPE_INT32:
case IR_TYPE_FLOAT:
case IR_TYPE_POINTER:
load32:
jit_push(iu, cond | (1 << 26) | (1 << 24) | (1 << 20) |
(R_VMSTACK << 16) | (reg << 12) |
jit_offset_to_imm12_U(iv->iv_reg));
break;
default:
parser_error(iu, "JIT: Can't load value typecode %d", it->it_code);
}
break;
case IR_VC_CONSTANT:
case IR_VC_GLOBALVAR:
jit_loadimm_cond(iu, ext == JIT_LOAD_EXT_SIGNED ?
value_get_const32(iu, iv) : value_get_const(iu, iv),
reg, jc, cond);
break;
case IR_VC_FUNCTION:
jit_loadimm_cond(iu, value_function_addr(iv), reg, jc, cond);
break;
default:
parser_error(iu, "JIT: Can't load value-class %d", iv->iv_class);
}
return reg;
}
/**
*
*/
static int __attribute__((warn_unused_result))
jit_loadvalue(ir_unit_t *iu, ir_valuetype_t vt, int reg, jitctx_t *jc)
{
return jit_loadvalue_cond(iu, vt, reg, jc, ARM_COND_AL, 0);
}
/**
*
*/
static int
jit_storevalue_reg(ir_unit_t *iu, ir_valuetype_t vt, int reg)
{
const ir_value_t *iv = value_get(iu, vt.value);
if(iv->iv_class == IR_VC_MACHINEREG)
return arm_machinereg(iv->iv_reg);
return reg;
}
/**
*
*/
static void
jit_storevalue_cond(ir_unit_t *iu, ir_valuetype_t vt, int reg, uint32_t cond)
{
const ir_value_t *iv = value_get(iu, vt.value);
const ir_type_t *it = type_get(iu, vt.type);
switch(iv->iv_class) {
case IR_VC_MACHINEREG:
if(arm_machinereg(iv->iv_reg) != reg) {
int Rd = arm_machinereg(iv->iv_reg);
int Rm = reg;
// MOV
jit_push(iu, cond | (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rm);
}
return;
case IR_VC_REGFRAME:
switch(legalize_type(it)) {
case IR_TYPE_INT1:
case IR_TYPE_INT8:
case IR_TYPE_INT16:
case IR_TYPE_INT32:
case IR_TYPE_FLOAT:
case IR_TYPE_POINTER:
jit_push(iu, cond | (1 << 26) | (1 << 24) |
(R_VMSTACK << 16) | (reg << 12) |
jit_offset_to_imm12_U(iv->iv_reg));
break;
default:
parser_error(iu, "JIT: Can't store value typecode %d", it->it_code);
}
break;
default:
parser_error(iu, "JIT: Can't store value-class %d", iv->iv_class);
}
}
static void
jit_storevalue(ir_unit_t *iu, ir_valuetype_t vt, int reg)
{
return jit_storevalue_cond(iu, vt, reg, ARM_COND_AL);
}
/**
*
*/
static int
jit_binop_check(ir_unit_t *iu, ir_instr_binary_t *ii)
{
const int binop = ii->op;
int typecode = legalize_type(type_get(iu, ii->lhs_value.type));
const ir_value_t *rhs;
switch(binop) {
case BINOP_SDIV:
case BINOP_UDIV:
if(!(iu->iu_jit_cpuflags & (1 << 17))) // Integer division
return 0;
if(typecode != IR_TYPE_INT32)
return 0;
break;
case BINOP_SREM:
case BINOP_UREM:
return 0;
case BINOP_ROL:
case BINOP_ROR:
rhs = value_get(iu, ii->rhs_value.value);
if(rhs->iv_class != IR_VC_CONSTANT)
return 0;
break;
case BINOP_ASHR:
if(typecode != IR_TYPE_INT32)
return 0;
break;
}
switch(typecode) {
case IR_TYPE_INT1:
case IR_TYPE_INT8:
case IR_TYPE_INT16:
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
break;
default:
return 0;
}
return 1;
}
/**
*
*/
static void
jit_binop(ir_unit_t *iu, ir_instr_binary_t *ii, jitctx_t *jc)
{
const int binop = ii->op;
const ir_value_t *rhs = value_get(iu, ii->rhs_value.value);
int Rd = R_TMPA;
int Rn = R_TMPA;
int Rm = R_TMPB;
Rd = jit_storevalue_reg(iu, ii->super.ii_ret, Rd);
Rn = jit_loadvalue(iu, ii->lhs_value, Rn, jc);
if(rhs->iv_class == IR_VC_CONSTANT) {
int32_t rc = value_get_const(iu, rhs);
int imm12;
switch(binop) {
case BINOP_SUB:
rc = -rc;
case BINOP_ADD:
if((imm12 = make_imm12(rc)) != -1) {
// ADD immediate
jit_pushal(iu, (1 << 25) | (1 << 23) | (Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
if((imm12 = make_imm12(-rc)) != -1) {
// SUB immediate
jit_pushal(iu, (1 << 25) | (1 << 22) | (Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
break;
case BINOP_OR:
if((imm12 = make_imm12(rc)) != -1) {
jit_pushal(iu, (1 << 25) | (1 << 24) | (1 << 23) |
(Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
break;
case BINOP_AND:
if((imm12 = make_imm12(rc)) != -1) {
jit_pushal(iu, (1 << 25) |
(Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
if((imm12 = make_imm12(~rc)) != -1) {
// BIC
jit_pushal(iu, (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22) |
(Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
break;
case BINOP_XOR:
if((imm12 = make_imm12(rc)) != -1) {
jit_pushal(iu, (1 << 25) | (1 << 21) |
(Rn << 16) | (Rd << 12) | imm12);
goto wb;
}
break;
case BINOP_SHL:
// LSL
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rn |
((rc & 0x1f) << 7));
goto wb;
case BINOP_LSHR:
if(rc != 0) {
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rn |
((rc & 0x1f) << 7) | (1 << 5));
goto wb;
}
break;
case BINOP_ASHR:
if(rc != 0) {
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rn |
((rc & 0x1f) << 7) | (1 << 6));
goto wb;
}
break;
case BINOP_ROL:
rc = 32 - rc;
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rn |
((rc & 0x1f) << 7) | (1 << 6) | (1 << 5));
goto wb;
case BINOP_ROR:
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 21) | (Rd << 12) | Rn |
((rc & 0x1f) << 7) | (1 << 6) | (1 << 5));
goto wb;
}
}
Rm = jit_loadvalue(iu, ii->rhs_value, Rm, jc);
switch(binop) {
case BINOP_ADD:
jit_push(iu, ARM_COND_AL | (1 << 23) |
(Rn << 16) | (Rd << 12) | Rm);
break;
case BINOP_SUB:
jit_push(iu, ARM_COND_AL | (1 << 22) |
(Rn << 16) | (Rd << 12) | Rm);
break;
case BINOP_MUL:
jit_push(iu, ARM_COND_AL | 0x90 |
(Rd << 16) | (Rm << 8) | Rn);
break;
case BINOP_OR:
jit_push(iu, ARM_COND_AL | (1 << 24) | (1 << 23) |
(Rn << 16) | (Rd << 12) | Rm);
break;
case BINOP_XOR:
jit_push(iu, ARM_COND_AL | (1 << 21) |
(Rn << 16) | (Rd << 12) | Rm);
break;
case BINOP_AND:
jit_push(iu, ARM_COND_AL |
(Rn << 16) | (Rd << 12) | Rm);
break;
case BINOP_SHL:
jit_push(iu, ARM_COND_AL | (1 << 24) | (1 << 23) | (1 << 21) |
(1 << 4) |
(Rm << 8) | (Rd << 12) | Rn);
break;
case BINOP_LSHR:
jit_push(iu, ARM_COND_AL | (1 << 24) | (1 << 23) | (1 << 21) |
(1 << 5) | (1 << 4) |
(Rm << 8) | (Rd << 12) | Rn);
break;
case BINOP_ASHR:
jit_push(iu, ARM_COND_AL | (1 << 24) | (1 << 23) | (1 << 21) |
(1 << 6) | (1 << 4) |
(Rm << 8) | (Rd << 12) | Rn);
break;
case BINOP_SDIV:
jit_push(iu, ARM_COND_AL | (1 << 26) | (1 << 25) | (1 << 24) | (1 << 20) |
0xf000 | (1 << 4) |
(Rm << 8) | (Rd << 16) | Rn);
break;
case BINOP_UDIV:
jit_push(iu, ARM_COND_AL | (1 << 26) | (1 << 25) | (1 << 24) | (1 << 20) |
(1 << 21) | 0xf000 | (1 << 4) |
(Rm << 8) | (Rd << 16) | Rn);
break;
default:
printf("armjit bad binop %d\n", binop);
abort();
}
wb:
jit_storevalue(iu, ii->super.ii_ret, Rd);
}
/**
*
*/
static int
jit_move_check(ir_unit_t *iu, ir_instr_move_t *ii)
{
int typecode = legalize_type(type_get(iu, ii->value.type));
switch(typecode) {
case IR_TYPE_INT8:
case IR_TYPE_INT16:
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
case IR_TYPE_FLOAT:
break;
default:
return 0;
}
return 1;
}
/**
*
*/
static void
jit_move(ir_unit_t *iu, ir_instr_move_t *ii, jitctx_t *jc)
{
int Rd = jit_storevalue_reg(iu, ii->super.ii_ret, R_TMPA);
int Rn = jit_loadvalue(iu, ii->value, Rd, jc);
jit_storevalue(iu, ii->super.ii_ret, Rn);
}
/**
*
*/
static int
jit_compute_ea(ir_unit_t *iu, ir_valuetype_t baseptr,
ir_valuetype_t value_offset,
int value_offset_multiply, int immediate_offset,
int preferred_reg,
jitctx_t *jc)
{
assert(preferred_reg != R_TMPB);
int regoff = -1, shift = 0;
if(value_offset.value >= 0) {
regoff = jit_loadvalue(iu, value_offset, R_TMPB, jc);
shift = ffs(value_offset_multiply) - 1;
if((1 << shift) != value_offset_multiply) {
jit_loadimm(iu, value_offset_multiply, R_TMPA, jc);
jit_push(iu, ARM_COND_AL | 0x90 |
(R_TMPB << 16) | (regoff << 8) | R_TMPA);
regoff = R_TMPB;
shift = 0;
}
}
int ea = jit_loadvalue(iu, baseptr, preferred_reg, jc);
if(regoff != -1) {
jit_pushal(iu, (1 << 23) | (ea << 16) | (preferred_reg << 12) |
(shift << 7) | regoff);
ea = preferred_reg;
}
if(immediate_offset) {
jit_push_add_imm(iu, preferred_reg, ea, immediate_offset, R_TMPB, jc);
ea = preferred_reg;
}
return ea;
}
/**
*
*/
static void
jit_lea(ir_unit_t *iu, ir_instr_lea_t *ii, jitctx_t *jc)
{
jit_storevalue(iu, ii->super.ii_ret,
jit_compute_ea(iu, ii->baseptr, ii->value_offset,
ii->value_offset_multiply, ii->immediate_offset,
R_TMPA, jc));
}
/**
*
*/
static int
jit_load_check(ir_unit_t *iu, ir_instr_load_t *ii)
{
const ir_type_t *retty = type_get(iu, ii->super.ii_ret.type);
switch(legalize_type(retty)) {
case IR_TYPE_INT1:
case IR_TYPE_INT8:
case IR_TYPE_INT16:
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
case IR_TYPE_FLOAT:
break;
default:
return 0;
}
return 1;
}
/**
*
*/
static void
jit_load(ir_unit_t *iu, ir_instr_load_t *ii, jitctx_t *jc)
{
int ea = jit_compute_ea(iu, ii->ptr, ii->value_offset,
ii->value_offset_multiply, ii->immediate_offset,
R_TMPA, jc);
int Rt = jit_storevalue_reg(iu, ii->super.ii_ret, R_TMPA);
if(ii->cast != -1) {
// Load + Cast
ir_type_t *pointee = type_get(iu, ii->load_type);
ir_type_t *retty = type_get(iu, ii->super.ii_ret.type);
switch(COMBINE3(legalize_type(retty), legalize_type(pointee), ii->cast)) {
case COMBINE3(IR_TYPE_INT32, IR_TYPE_INT8, CAST_ZEXT):
// LDRB
jit_pushal(iu, (1 << 26) | (1 << 25) | (1 << 24) | (1 << 23) |
(1 << 22) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | ea);
break;
case COMBINE3(IR_TYPE_INT32, IR_TYPE_INT8, CAST_SEXT):
// LDRSB
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | 0xd0 | ea);
break;
case COMBINE3(IR_TYPE_INT32, IR_TYPE_INT16, CAST_ZEXT):
// LDRH
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | 0xb0 | ea);
break;
case COMBINE3(IR_TYPE_INT32, IR_TYPE_INT16, CAST_SEXT):
// LDRSH
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | 0xf0 | ea);
break;
}
} else {
ir_type_t *pointee = type_get(iu, ii->super.ii_ret.type);
switch(legalize_type(pointee)) {
default:
fprintf(stderr, "jit: Bad pointer type in load @ %d\n", __LINE__);
abort();
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
case IR_TYPE_FLOAT:
// LDR
jit_push(iu, ARM_COND_AL | (1 << 26) | (1 << 25) | (1 << 24) |
(1 << 23) | (1 << 20) | (R_MEM << 16) | (Rt << 12) | ea);
break;
case IR_TYPE_INT16:
// LDRH
jit_pushal(iu, (1 << 24) | (1 << 23) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | 0xb0 | ea);
break;
case IR_TYPE_INT8:
case IR_TYPE_INT1:
// LDRB
jit_pushal(iu, (1 << 26) | (1 << 25) | (1 << 24) | (1 << 23) |
(1 << 22) | (1 << 20) |
(R_MEM << 16) | (Rt << 12) | ea);
break;
}
}
jit_storevalue(iu, ii->super.ii_ret, Rt);
}
/**
*
*/
static int
jit_store_check(ir_unit_t *iu, ir_instr_store_t *ii)
{
const ir_type_t *ty = type_get(iu, ii->value.type);
switch(legalize_type(ty)) {
case IR_TYPE_INT1:
case IR_TYPE_INT8:
case IR_TYPE_INT16:
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
case IR_TYPE_FLOAT:
break;
default:
return 0;
}
return 1;
}
/**
*
*/
static void
jit_store(ir_unit_t *iu, ir_instr_store_t *ii, jitctx_t *jc)
{
int ea = jit_loadvalue(iu, ii->ptr, R_TMPA, jc);
if(ii->immediate_offset) {
jit_push_add_imm(iu, R_TMPA, ea, ii->immediate_offset, R_TMPB, jc);
ea = R_TMPA;
}
int Rt = jit_loadvalue(iu, ii->value, R_TMPB, jc);
switch(legalize_type(type_get(iu, ii->value.type))) {
default:
fprintf(stderr, "jit: Bad pointer type in store @ %d\n", __LINE__);
abort();
case IR_TYPE_INT32:
case IR_TYPE_POINTER:
case IR_TYPE_FLOAT:
// STR
jit_push(iu, ARM_COND_AL | (1 << 26) | (1 << 25) | (1 << 24) |
(1 << 23) | (R_MEM << 16) | (Rt << 12) | ea);
break;
case IR_TYPE_INT16:
// STRH
jit_pushal(iu, (1 << 24) | (1 << 23) |
(R_MEM << 16) | (Rt << 12) | 0xb0 | ea);
break;
case IR_TYPE_INT1:
case IR_TYPE_INT8:
// STRB
jit_pushal(iu, (1 << 26) | (1 << 25) | (1 << 24) | (1 << 23) |
(1 << 22) |
(R_MEM << 16) | (Rt << 12) | ea);