From 8ab50dddcf34a6fda1dedd5a4034ffcab37a6aaf Mon Sep 17 00:00:00 2001 From: fengfeng <153487255+fengfeng09@users.noreply.github.com> Date: Mon, 15 Apr 2024 17:01:15 +0800 Subject: [PATCH] [SelectionDAG] Propagate Disjoint flag. (#88370) Signed-off-by: feng.feng --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 ++- .../CodeGen/X86/propagate-disjoint-in-shl-or.ll | 15 +++++++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d9c6c28d5dac96..dbbe8d9193c25c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9530,7 +9530,8 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) { SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT); SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC); SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1); - return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2); + return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2, + LogicOp->getFlags()); } /// Handle transforms common to the three shifts, when the shift amount is a diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 4939976b8e2875..c938b3996be393 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -544,7 +544,8 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op, if (!C.isSubsetOf(DemandedBits)) { EVT VT = Op.getValueType(); SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT); - SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); + SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC, + Op->getFlags()); return TLO.CombineTo(Op, NewOp); } diff --git a/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll new file mode 100644 index 00000000000000..e38840f3e46106 --- /dev/null +++ b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll @@ -0,0 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64 %s -start-before=x86-isel -o - | FileCheck %s + +define i32 @add_shl_or_disjoint(i32 %x) { +; CHECK-LABEL: add_shl_or_disjoint: +; CHECK: # %bb.0: +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: leal 165036822(,%rdi,4), %eax +; CHECK-NEXT: retq + %or = or disjoint i32 %x, 4027584529 + %shl = shl i32 %or, 2 + %add = add i32 %shl, 1234567890 + ret i32 %add +} +