-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathproblema3.qsf
92 lines (90 loc) · 4.65 KB
/
problema3.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:05:09 June 18, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# problema3_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY circuito_principal
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:05:09 JUNE 18, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name VERILOG_FILE display_segmentos.v
set_global_assignment -name VERILOG_FILE controlador_memoria.v
set_global_assignment -name VERILOG_FILE controlador_principal.v
set_global_assignment -name VERILOG_FILE multiplexador.v
set_global_assignment -name VERILOG_FILE vericador_valor.v
set_global_assignment -name VERILOG_FILE acumulador.v
set_global_assignment -name VERILOG_FILE controlador_teclado.v
set_global_assignment -name VERILOG_FILE gerador_codificador.v
set_global_assignment -name VERILOG_FILE temporizador.v
set_global_assignment -name VERILOG_FILE circuito_principal.v
set_global_assignment -name VERILOG_FILE divisor_clock.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_multiplexador.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_temporizador.vwf
set_global_assignment -name VERILOG_FILE decodificador.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_circuitoPrincipal.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_controlador_teclado.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_gerador_cod.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_controlador_principal.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_acumulador.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Teste_verifica_Valor.vwf
set_location_assignment PIN_12 -to clk
set_location_assignment PIN_88 -to displays[3]
set_location_assignment PIN_66 -to displays[2]
set_location_assignment PIN_68 -to displays[1]
set_location_assignment PIN_37 -to displays[0]
set_location_assignment PIN_42 -to moedas[1]
set_location_assignment PIN_40 -to moedas[0]
set_location_assignment PIN_52 -to tecla[3]
set_location_assignment PIN_50 -to tecla[2]
set_location_assignment PIN_48 -to tecla[1]
set_location_assignment PIN_44 -to tecla[0]
set_location_assignment PIN_55 -to liberar
set_location_assignment PIN_54 -to devolver_moedas
set_global_assignment -name VERILOG_FILE multiplexadorSegmentos.v
set_location_assignment PIN_90 -to segmentos[7]
set_location_assignment PIN_70 -to segmentos[6]
set_location_assignment PIN_41 -to segmentos[5]
set_location_assignment PIN_98 -to segmentos[4]
set_location_assignment PIN_100 -to segmentos[3]
set_location_assignment PIN_92 -to segmentos[2]
set_location_assignment PIN_39 -to segmentos[1]
set_location_assignment PIN_96 -to segmentos[0]