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[Bug] Unsupported CPU on SpacemiT K1 Otca-core X60(RV64GCVB),RVA22, #17508
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@JieGH , I look into this, let's fix it. In the meanwhile, latest llvm is a must to have for RISC-V targets (18.x , 19.x is fine), but also could please enable orcjit executor (which is experimental, under
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Hi @cbalint13 , thanks for the miracle you bring. It works now. I attached the target I used here and the version of my time and llvm. I will test the TVM with a more extensive test later. Privious error message: Unsupported CPU type!
UNREACHABLE executed at /home/USER/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp:1080!
Aborted Solution: enable LLVM’s Orc JIT (On-Request Compilation) engine target = "llvm -jit=orcjit -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+a,+c,+d,+f,+m" Target kind: llvm
Target options: {"mtriple": "riscv64-linux-gnu"}
LLVM config path: /usr/local/bin/llvm-config
llc --version output:
LLVM (http://llvm.org/):
LLVM version 19.1.3
Optimized build with assertions.
Default target: riscv64-linux-gnu
Host CPU: generic-rv64
Registered Targets:
riscv32 - 32-bit RISC-V
riscv64 - 64-bit RISC-V |
Hi @JieGH ,
Thanks a lot for your time and the feedback ! It is not a miracle, but I will open a PR to propose promotion of Please let me know any of your performance test, you are welcome to report it here, I am personally interested in the riscv targets. On my personal task list there is a RVV tensorization proposal for metaschedule/autoschedule, a preliminary integration with benchmarks for v0.7.1 and v1.0 RVV variants are here: https://github.com/cbalint13/rvv-kernels |
Expected Behavior
After building TVM 0.18.0 with LLVM 19.1.3, I expect TVM to generate RISC-V compatible code that executes without errors related to unsupported CPU types. The build should allow the execution of a basic TVM Python example on a Banana Pi K1 board, with the
riscv64-linux-gnu
target specified in the configuration.Actual Behavior
Upon running a simple TVM example with LLVM 19.1.3 and TVM 0.18.0 on the Banana Pi K1, I encounter the following error message:
In the TVM logs, there is also a warning that native vector bits are set to 128 for RISC-V, which could be relevant to the issue. The error persists despite multiple rebuilds of both LLVM and TVM, with adjusted configurations and target-specific flags to ensure compatibility with the RISC-V architecture on this board.
The error appears to stem from LLVM’s RuntimeDyldELF.cpp file, and recent threads, such as LLVM Issue #58652 and Halide Issue #7078, mention related problems that were resolved in newer LLVM releases, motivating my decision to upgrade from LLVM 15.0.7 to 19.1.3.
Environment
Steps to Reproduce
Additional Notes and Troubleshooting
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