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Utilization factor and aspect ratio
- Define W, H of core and die
- Utilization Factor = (Area occupied by netlist)/(Total area of the core)
- Usually we aim for 50-60 % Utilization Factor
- Aspect Ratio = Height/ Width
- Define W, H of core and die
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Define locations of pre-placed cells (macros and IPs ?)
- IPs/ blocks have user-defined locations and hence placed before automated PnR and are called as pre-placed cells
- Automated PnR tools places the remaining logical cells in the design onto the chip
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Decaps
- Decouples the circuit from the VDD rail
- Reduce Zpdn for the required frequencies of operation
- Serve as a charge reservoir for the switching current demands that the VDD rail cannot satisfy.
- Surround pre-placed cells with Decaps to compensate for the switching current demands (di/dt)
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Power Planning
- SSN
- L*di/dt
- Discharging : Ground bounce
- Charging : Voltage Droop
- Solution: Reduce the Vdd/ Vss parasitics ->
- Power grid
- Multiple VDD, VSS pins/ balls
- L*di/dt
- SSN
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Pin Placement
- Usually: East -> West, North -> South, {East, North} -> {West, South}
- Pin ordering is random (unless we specify explicitly ?)
- Front-End to Back-End team communication/ handshaking needed for optimal pin placement
- CLK ports/ pins are usually bigger to reduce the clk net resistance
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Logical Cell placement blockage - so that no cells are placed by the PnR tool inside the IP blocks/ macro area.
Now Floorplan is ready for PnR
- To run the floorplan creation, execute the following command from the OpenLANE shell:
run_floorplan
- To view the floor plan in Magic:
1) cd to the floorplan results directory for the current run: openlane/designs/<design-name>/runs/<time-stamp>/results/floorplan 2) magic -T $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read ./picorv32a.floorplan.def &
Floorplan view in Magic (FP_IO_MODE=1, Random equidistant mode) ![]() |
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Floorplan Zoomed in at (0,0) ![]() |
FP_IO_MODE=0 (Matching mode) ![]() |
FP_IO_MODE=1 Zoomed![]() |
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Bind netlist with physical cells
- Library files
- Shape, dimension info, power & timing/ delay info
- Various flavors of all available std cells
- Library files
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Placement
- The location of pre-placed cells are fixed and PnR tools will not place any cells inside that area.
- Initial global placement based on the input, output pins to reduce wire lengths
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Optimize placement
- Ensure that Signal Integrity is maintained
- Estimate the wire length and capacitance and insert repeaters/ buffers
- MaxTrans delay/ signal slew
- Ensure that Signal Integrity is maintained
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Congestion aware placement using RePlAce followed by detailed placement using OpenDP
- Global placement: HPWL (Half-Parameter Wire Length) based
- The
run_placement
command runs the global placement followed by detailed placement. - First the global placement happens, where the main objective is to reduce the wire length. Algorithm used is Half-Parameter Wire Length (HPWL).
- Then detailed placement is performed to legalize the globally placed components.
run_placement![]() |
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Layout after placement![]() |
Layout after placement (Zoomed) ![]() |
Library
- Std cells of different:
- logic functionality
- size/ drive strengths
- threshold voltages
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Inputs for Cell Design Flow
From foundry, PDKs:- DRC, LVS rules (eg: lambda-based design rules)
- SPICE modelsfor the NMOS & PMOS devices
- Library and user-defined specifications
- Cell height (separation b/w VDD and GND rails) must be maintained
- Cell width is determined by the drive strengths required
- Supply voltage
- Metal layers requirements
- Pin locations
- Drawn gate-length
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Design Steps
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Circuit Design
- Transistor sizing based on current drive, voltage transfer and other performance/ quality parameter requirements
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Layout Design
- Art of layout - Euler's path and stick diagram
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Characterization
- Read the nmos, pmos models
- Read the extracted spice netlist
- Recognize the behaviour of the cell
- Read the sub-circuits
- Attach the power sources
- Apply the stimulus
- Provide the necessary output capacitance
- Provide the necessary simulation commands
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Now, feed in all this to GUNA characterization tool --> to generate Timing, noise, power .libs, function
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Outputs
- CDL (Circuit Description Language)
- GDSII, LEF (dimensions), extracted spice netlist (.cir)
- Timing, noise, power .libs, function
Timing characterization parameters
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Timing threshold definitions
Parameter Usually used values slew_low_rise_thr 10%, 20% slew_high_rise_thr 90%, 80% slew_low_fall_thr 10%, 20% slew_high_fall_thr 90%, 80% in_rise_thr 50% in_fall_thr 50% out_rise_thr 50% out_fall_thr 50% -
Propagation delay
- propagation delay = time(out_thr) - time(in_thr)
- Problematic cases:
- Choice of threshold levels
- Large RC delays (due to improper designs and/ or large loads, long routes)
- Problematic cases:
- propagation delay = time(out_thr) - time(in_thr)
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Transition time
- t_rise = time(slew_high_rise_thr) - time(slew_low_rise_thr)
- t_fall = time(slew_low_fall_thr) - time(slew_high_fall_thr)