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vivado_16052.backup.log
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vivado_16052.backup.log
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Wed Dec 14 21:54:32 2022
# Process ID: 16052
# Current directory: C:/Xilinx/projects/Bidirectional_Transmitter
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16504 C:\Xilinx\projects\Bidirectional_Transmitter\Bidirectional_Transmitter.xpr
# Log file: C:/Xilinx/projects/Bidirectional_Transmitter/vivado.log
# Journal file: C:/Xilinx/projects/Bidirectional_Transmitter\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 918.559 ; gain = 180.844
update_compile_order -fileset sources_1
open_bd_design {C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_50M
Adding cell -- xilinx.com:module_ref:UART_Reciever:1.0 - UART_Reciever_0
Adding cell -- xilinx.com:module_ref:UART_Transmitter:1.0 - UART_Transmitter_0
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <Bidirectional_Transmitter> from BD file <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
open_bd_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1011.941 ; gain = 88.438
close [ open C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/new/gpio_parse.v w ]
add_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/new/gpio_parse.v
update_compile_order -fileset sources_1
startgroup
set_property -dict [list CONFIG.C_GPIO_WIDTH {10}] [get_bd_cells axi_gpio_0]
endgroup
create_bd_cell -type module -reference gpio_parse gpio_parse_0
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
delete_bd_objs [get_bd_nets axi_gpio_0_gpio_io_o]
connect_bd_net [get_bd_pins UART_Transmitter_0/tx_axgpio] [get_bd_pins gpio_parse_0/tx_gpio]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins gpio_parse_0/gpio_in]
WARNING: [BD 41-1306] The connection to interface pin /axi_gpio_0/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
update_compile_order -fileset sources_1
regenerate_bd_layout
startgroup
make_bd_pins_external [get_bd_pins gpio_parse_0/din_gpio]
endgroup
set_property name din_gpio [get_bd_ports din_gpio_0]
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
regenerate_bd_layout
validate_bd_design
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
reset_run synth_1
reset_run Bidirectional_Transmitter_axi_gpio_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 2.719 MB.
[Wed Dec 14 22:06:12 2022] Launched Bidirectional_Transmitter_axi_gpio_0_0_synth_1, Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_axi_gpio_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_axi_gpio_0_0_synth_1/runme.log
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:06:13 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 1186.102 ; gain = 114.039
reset_run synth_1
reset_run Bidirectional_Transmitter_axi_gpio_0_0_synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0
INFO: [Device 21-403] Loading part xc7z007sclg400-1
create_bd_cell: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1312.816 ; gain = 126.715
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {/processing_system7_0/FCLK_CLK0 (50 MHz)} Clk_slave {Auto} Clk_xbar {/processing_system7_0/FCLK_CLK0 (50 MHz)} Master {/processing_system7_0/M_AXI_GP0} Slave {/xadc_wiz_0/s_axi_lite} intc_ip {/ps7_0_axi_periph} master_apm {0}} [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
</xadc_wiz_0/s_axi_lite/Reg> is being mapped into </processing_system7_0/Data> at <0x43C00000 [ 64K ]>
validate_bd_design
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
regenerate_bd_layout
startgroup
set_property -dict [list CONFIG.XADC_STARUP_SELECTION {channel_sequencer} CONFIG.ADC_CONVERSION_RATE {962} CONFIG.OT_ALARM {false} CONFIG.USER_TEMP_ALARM {false} CONFIG.VCCINT_ALARM {false} CONFIG.VCCAUX_ALARM {false} CONFIG.ENABLE_VCCPINT_ALARM {false} CONFIG.ENABLE_VCCPAUX_ALARM {false} CONFIG.ENABLE_VCCDDRO_ALARM {false} CONFIG.SEQUENCER_MODE {Continuous} CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} CONFIG.CHANNEL_ENABLE_VP_VN {true}] [get_bd_cells xadc_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 {true} CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} CONFIG.CHANNEL_ENABLE_VAUXP12_VAUXN12 {true} CONFIG.CHANNEL_ENABLE_VAUXP13_VAUXN13 {true} CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true}] [get_bd_cells xadc_wiz_0]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vp_Vn]
endgroup
set_property name Vp_Vn [get_bd_intf_ports Vp_Vn_0]
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux0]
endgroup
set_property name Vaux0 [get_bd_intf_ports Vaux0_0]
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux1]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux5]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux6]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux8]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux9]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux12]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux13]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux15]
endgroup
set_property name Vaux1 [get_bd_intf_ports Vaux1_0]
set_property name Vaux5 [get_bd_intf_ports Vaux5_0]
set_property name Vaux6 [get_bd_intf_ports Vaux6_0]
set_property name Vaux8 [get_bd_intf_ports Vaux8_0]
set_property name Vaux9 [get_bd_intf_ports Vaux9_0]
set_property name Vaux12 [get_bd_intf_ports Vaux12_0]
set_property name Vaux13 [get_bd_intf_ports Vaux13_0]
set_property name Vaux15 [get_bd_intf_ports Vaux15_0]
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
regenerate_bd_layout
regenerate_bd_layout
validate_bd_design
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
regenerate_bd_layout
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
launch_runs impl_1 -to_step write_bitstream -jobs 7
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 2.719 MB.
[Wed Dec 14 22:18:35 2022] Launched Bidirectional_Transmitter_axi_gpio_0_0_synth_1, Bidirectional_Transmitter_gpio_parse_0_0_synth_1, Bidirectional_Transmitter_xbar_0_synth_1, Bidirectional_Transmitter_xadc_wiz_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_axi_gpio_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_axi_gpio_0_0_synth_1/runme.log
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
Bidirectional_Transmitter_xbar_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_xbar_0_synth_1/runme.log
Bidirectional_Transmitter_xadc_wiz_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_xadc_wiz_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:18:35 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 1496.496 ; gain = 46.871
launch_sdk -workspace C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk -hwspec C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk -hwspec C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v] -no_script -reset -force -quiet
remove_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
file delete -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
make_wrapper -files [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -top
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
add_files -norecurse C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
generate_target all [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
launch_runs -jobs 7 Bidirectional_Transmitter_gpio_parse_0_0_synth_1
[Wed Dec 14 22:21:34 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
export_simulation -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -directory C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/sim_scripts -ip_user_files_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files -ipstatic_source_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/modelsim} {questa=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/questa} {riviera=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/riviera} {activehdl=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property top Bidirectional_Transmitter_wrapper [current_fileset]
update_compile_order -fileset sources_1
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 22:22:18 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:22:18 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 22:23:01 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:23:01 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 22:23:54 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:23:54 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
update_module_reference Bidirectional_Transmitter_gpio_parse_0_0
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_gpio_parse_0_0 from gpio_parse_v1_0 1.0 to gpio_parse_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 4.250 MB.
[Wed Dec 14 22:25:13 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:25:13 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1882.594 ; gain = 42.566
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 22:28:41 2022] Launched synth_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:28:41 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 22:31:34 2022] Launched synth_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 22:31:34 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
startgroup
set_property -dict [list CONFIG.NUM_MI {3}] [get_bd_cells ps7_0_axi_periph]
endgroup
connect_bd_net [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
regenerate_bd_layout
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
validate_bd_design
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
reset_run synth_1
reset_run Bidirectional_Transmitter_xbar_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 4.250 MB.
[Wed Dec 14 23:02:11 2022] Launched Bidirectional_Transmitter_xbar_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_xbar_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_xbar_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 23:02:11 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1947.762 ; gain = 41.945
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_gpio_parse_0_0
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_gpio_parse_0_0 from gpio_parse_v1_0 1.0 to gpio_parse_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
generate_target all [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
catch { config_ip_cache -export [get_ips -all Bidirectional_Transmitter_auto_pc_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 4.844 MB.
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
launch_runs -jobs 7 Bidirectional_Transmitter_gpio_parse_0_0_synth_1
[Wed Dec 14 23:58:20 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
export_simulation -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -directory C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/sim_scripts -ip_user_files_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files -ipstatic_source_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/modelsim} {questa=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/questa} {riviera=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/riviera} {activehdl=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Wed Dec 14 23:58:45 2022] Launched Bidirectional_Transmitter_gpio_parse_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_gpio_parse_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_gpio_parse_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Wed Dec 14 23:58:46 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 4.844 MB.
[Thu Dec 15 00:40:51 2022] Launched Bidirectional_Transmitter_UART_Reciever_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Reciever_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Reciever_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Thu Dec 15 00:40:51 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 2039.016 ; gain = 39.309
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 4.844 MB.
[Thu Dec 15 00:48:16 2022] Launched Bidirectional_Transmitter_UART_Reciever_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Reciever_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Reciever_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Thu Dec 15 00:48:16 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 2084.840 ; gain = 42.172
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
exit
INFO: [Common 17-206] Exiting Vivado at Thu Dec 15 00:57:42 2022...