From 35b9867dc4e06f929dc945127cb9bebd95701ede Mon Sep 17 00:00:00 2001 From: Lance Lui Date: Mon, 5 Aug 2024 22:13:50 +0000 Subject: [PATCH] Add AMD PMC/U support --- src/data.rs | 3 + src/data/amd_genoa_perf_events.rs | 24 ++++++ src/data/amd_milan_perf_events.rs | 35 ++++++++ src/data/amd_perf_events.rs | 135 ++++++++++++++++++++++++++++++ src/data/perf_stat.rs | 12 +++ 5 files changed, 209 insertions(+) create mode 100644 src/data/amd_genoa_perf_events.rs create mode 100644 src/data/amd_milan_perf_events.rs create mode 100644 src/data/amd_perf_events.rs diff --git a/src/data.rs b/src/data.rs index b14482f9..39d6feb6 100644 --- a/src/data.rs +++ b/src/data.rs @@ -10,6 +10,9 @@ cfg_if::cfg_if! { pub mod intel_perf_events; pub mod intel_icelake_perf_events; pub mod intel_sapphire_rapids_perf_events; + pub mod amd_perf_events; + pub mod amd_genoa_perf_events; + pub mod amd_milan_perf_events; } } pub mod interrupts; diff --git a/src/data/amd_genoa_perf_events.rs b/src/data/amd_genoa_perf_events.rs new file mode 100644 index 00000000..2d9d1f17 --- /dev/null +++ b/src/data/amd_genoa_perf_events.rs @@ -0,0 +1,24 @@ +use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType}; + +static STALL_BACKEND_PKC: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Backend-Stalls", + config: 0x100001ea0, +}; +static CYCLES: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Cycles", + config: 0x0076, +}; + +lazy_static! { + pub static ref GENOA_CTRS: Vec> = [ + NamedCtr { + name: "stall_backend_pkc", + nrs: vec![STALL_BACKEND_PKC], + drs: vec![CYCLES], + scale: 167 //~= 1000/6 + }, + ] + .to_vec(); +} \ No newline at end of file diff --git a/src/data/amd_milan_perf_events.rs b/src/data/amd_milan_perf_events.rs new file mode 100644 index 00000000..50209cc7 --- /dev/null +++ b/src/data/amd_milan_perf_events.rs @@ -0,0 +1,35 @@ +use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType}; + +static STALL_BACKEND_PKC1: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Backend-Stalls-1", + config: 0xf7ae, +}; +static STALL_BACKEND_PKC2: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Backend-Stalls-2", + config: 0x27af, +}; +static CYCLES: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Cycles", + config: 0x0076, +}; + +lazy_static! { + pub static ref MILAN_CTRS: Vec> = [ + NamedCtr { + name: "stall_backend_pkc1", + nrs: vec![STALL_BACKEND_PKC1], + drs: vec![CYCLES], + scale: 1000 + }, + NamedCtr { + name: "stall_backend_pkc2", + nrs: vec![STALL_BACKEND_PKC2], + drs: vec![CYCLES], + scale: 1000 + }, + ] + .to_vec(); +} \ No newline at end of file diff --git a/src/data/amd_perf_events.rs b/src/data/amd_perf_events.rs new file mode 100644 index 00000000..b492aa47 --- /dev/null +++ b/src/data/amd_perf_events.rs @@ -0,0 +1,135 @@ +use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType}; + +// amd events +static INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Instructions", + config: 0x00c0, +}; +static CYCLES: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Cycles", + config: 0x0076, +}; +static BRANCHES: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Branches", + config: 0x00c3, +}; +static L1_DATA: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "L1-Data", + config: 0xff44, +}; +static L1_INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "L1-Instructions", + config: 0x1060, +}; +static L2: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "L2", + config: 0x0964, +}; +static L3: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "L3", + config: 0x0843, +}; +static STALL_FRONTEND_PKC: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Frontend-Stalls", + config: 0x00a9, +}; +static INSTRUCTION_TLB: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Instruction-TLB", + config: 0x0084, +}; +static INSTRUCTION_TLB_TW: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Instruction-TLB-TW", + config: 0x0f85, +}; +static DATA_TLB: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Data-TLB", + config: 0xff45, +}; +static DATA_TLB_TW: NamedTypeCtr = NamedTypeCtr { + perf_type: PerfType::RAW, + name: "Data-TLB-TW", + config: 0xf045, +}; + +lazy_static! { + pub static ref PERF_LIST: Vec> = [ + NamedCtr { + name: "ipc", + nrs: vec![INSTRUCTIONS], + drs: vec![CYCLES], + scale: 1 + }, + NamedCtr { + name: "branch-mpki", + nrs: vec![BRANCHES], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "data-l1-mpki", + nrs: vec![L1_DATA], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "inst-l1-mpki", + nrs: vec![L1_INSTRUCTIONS], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "l2-mpki", + nrs: vec![L2], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "l3-mpki", + nrs: vec![L3], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "stall_frontend_pkc", + nrs: vec![STALL_FRONTEND_PKC], + drs: vec![CYCLES], + scale: 1000 + }, + NamedCtr { + name: "inst-tlb-mpki", + nrs: vec![INSTRUCTION_TLB], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "inst-tlb-tw-mpki", + nrs: vec![INSTRUCTION_TLB_TW], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "data-tlb-mpki", + nrs: vec![DATA_TLB], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + NamedCtr { + name: "data-tlb-tw-pki", + nrs: vec![DATA_TLB_TW], + drs: vec![INSTRUCTIONS], + scale: 1000 + }, + ] + .to_vec(); +} \ No newline at end of file diff --git a/src/data/perf_stat.rs b/src/data/perf_stat.rs index e6970827..351a46b5 100644 --- a/src/data/perf_stat.rs +++ b/src/data/perf_stat.rs @@ -19,6 +19,8 @@ use crate::data::grv_perf_events; use { crate::data::intel_icelake_perf_events::ICX_CTRS, crate::data::intel_perf_events, crate::data::intel_sapphire_rapids_perf_events::SPR_CTRS, crate::data::utils::get_cpu_info, + crate::data::amd_genoa_perf_events::GENOA_CTRS, crate::data::amd_perf_events, + crate::data::amd_milan_perf_events::MILAN_CTRS, indexmap::IndexMap, }; @@ -140,6 +142,16 @@ impl CollectData for PerfStatRaw { "Intel(R) Xeon(R) Platinum 8488C" => SPR_CTRS.to_vec(), _ => Vec::new(), }; + } else if cpu_info.vendor == "AuthenticAMD" { + warn!("Event multiplexing may result in bad PMU data."); //TODO: mitigate bad PMU data on AMD instances + perf_list = amd_perf_events::PERF_LIST.to_vec(); + + /* Get Model specific events */ + platform_specific_counter = match cpu_info.model_name.as_str() { + "AMD EPYC 9R14" => GENOA_CTRS.to_vec(), + "AMD EPYC 7R13 Processor" => MILAN_CTRS.to_vec(), + _ => Vec::new(), + }; } else { return Err(PDError::CollectorPerfUnsupportedCPU.into()); }