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mm_reset_hw.tcl
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mm_reset_hw.tcl
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# TCL File Generated by Component Editor 15.0
# Wed Mar 28 20:01:57 PDT 2018
# DO NOT MODIFY
#
# mm_reset "Memory Mapped Reset" v1.0
# 2018.03.28.20:01:57
#
#
#
# request TCL package from ACDS 15.0
#
package require -exact qsys 15.0
#
# module mm_reset
#
set_module_property DESCRIPTION ""
set_module_property NAME mm_reset
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Memory Mapped Reset"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL mm_reset
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pixel_cluster.sv SYSTEM_VERILOG PATH pixel_cluster/pixel_cluster.sv
add_fileset_file mm_reset.sv SYSTEM_VERILOG PATH mm_reset/mm_reset.sv TOP_LEVEL_FILE
#
# parameters
#
add_parameter N_REGS POSITIVE 4 ""
set_parameter_property N_REGS DEFAULT_VALUE 4
set_parameter_property N_REGS DISPLAY_NAME N_REGS
set_parameter_property N_REGS WIDTH ""
set_parameter_property N_REGS TYPE POSITIVE
set_parameter_property N_REGS ENABLED false
set_parameter_property N_REGS UNITS None
set_parameter_property N_REGS ALLOWED_RANGES 1:2147483647
set_parameter_property N_REGS DESCRIPTION ""
set_parameter_property N_REGS HDL_PARAMETER true
add_parameter CYCLES POSITIVE 100 ""
set_parameter_property CYCLES DEFAULT_VALUE 100
set_parameter_property CYCLES DISPLAY_NAME CYCLES
set_parameter_property CYCLES WIDTH ""
set_parameter_property CYCLES TYPE POSITIVE
set_parameter_property CYCLES UNITS None
set_parameter_property CYCLES ALLOWED_RANGES 1:2147483647
set_parameter_property CYCLES DESCRIPTION ""
set_parameter_property CYCLES HDL_PARAMETER true
add_parameter ADDR_BITS POSITIVE 2 ""
set_parameter_property ADDR_BITS DEFAULT_VALUE 2
set_parameter_property ADDR_BITS DISPLAY_NAME ADDR_BITS
set_parameter_property ADDR_BITS WIDTH ""
set_parameter_property ADDR_BITS TYPE POSITIVE
set_parameter_property ADDR_BITS ENABLED false
set_parameter_property ADDR_BITS UNITS None
set_parameter_property ADDR_BITS ALLOWED_RANGES 1:2147483647
set_parameter_property ADDR_BITS DESCRIPTION ""
set_parameter_property ADDR_BITS HDL_PARAMETER true
add_parameter REG_BITS INTEGER 32
set_parameter_property REG_BITS DEFAULT_VALUE 32
set_parameter_property REG_BITS DISPLAY_NAME REG_BITS
set_parameter_property REG_BITS TYPE INTEGER
set_parameter_property REG_BITS ENABLED false
set_parameter_property REG_BITS UNITS None
set_parameter_property REG_BITS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property REG_BITS HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point mm
#
add_interface mm avalon end
set_interface_property mm addressUnits WORDS
set_interface_property mm associatedClock clock
set_interface_property mm associatedReset reset
set_interface_property mm bitsPerSymbol 8
set_interface_property mm burstOnBurstBoundariesOnly false
set_interface_property mm burstcountUnits WORDS
set_interface_property mm explicitAddressSpan 0
set_interface_property mm holdTime 0
set_interface_property mm linewrapBursts false
set_interface_property mm maximumPendingReadTransactions 0
set_interface_property mm maximumPendingWriteTransactions 0
set_interface_property mm readLatency 0
set_interface_property mm readWaitTime 1
set_interface_property mm setupTime 0
set_interface_property mm timingUnits Cycles
set_interface_property mm writeWaitTime 0
set_interface_property mm ENABLED true
set_interface_property mm EXPORT_OF ""
set_interface_property mm PORT_NAME_MAP ""
set_interface_property mm CMSIS_SVD_VARIABLES ""
set_interface_property mm SVD_ADDRESS_GROUP ""
add_interface_port mm mm_address address Input ADDR_BITS
add_interface_port mm mm_byteenable byteenable Input REG_BITS/8
add_interface_port mm mm_read read Input 1
add_interface_port mm mm_write write Input 1
add_interface_port mm mm_readdata readdata Output REG_BITS
add_interface_port mm mm_writedata writedata Input REG_BITS
set_interface_assignment mm embeddedsw.configuration.isFlash 0
set_interface_assignment mm embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment mm embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment mm embeddedsw.configuration.isPrintableDevice 0
#
# connection point timed_reset_0
#
add_interface timed_reset_0 reset start
set_interface_property timed_reset_0 associatedClock clock
set_interface_property timed_reset_0 associatedDirectReset ""
set_interface_property timed_reset_0 associatedResetSinks ""
set_interface_property timed_reset_0 synchronousEdges DEASSERT
set_interface_property timed_reset_0 ENABLED true
set_interface_property timed_reset_0 EXPORT_OF ""
set_interface_property timed_reset_0 PORT_NAME_MAP ""
set_interface_property timed_reset_0 CMSIS_SVD_VARIABLES ""
set_interface_property timed_reset_0 SVD_ADDRESS_GROUP ""
add_interface_port timed_reset_0 reset0 reset Output 1
#
# connection point timed_reset_1
#
add_interface timed_reset_1 reset start
set_interface_property timed_reset_1 associatedClock clock
set_interface_property timed_reset_1 associatedDirectReset ""
set_interface_property timed_reset_1 associatedResetSinks ""
set_interface_property timed_reset_1 synchronousEdges DEASSERT
set_interface_property timed_reset_1 ENABLED true
set_interface_property timed_reset_1 EXPORT_OF ""
set_interface_property timed_reset_1 PORT_NAME_MAP ""
set_interface_property timed_reset_1 CMSIS_SVD_VARIABLES ""
set_interface_property timed_reset_1 SVD_ADDRESS_GROUP ""
add_interface_port timed_reset_1 reset1 reset Output 1
#
# connection point persistent_reset_0
#
add_interface persistent_reset_0 reset start
set_interface_property persistent_reset_0 associatedClock clock
set_interface_property persistent_reset_0 associatedDirectReset ""
set_interface_property persistent_reset_0 associatedResetSinks ""
set_interface_property persistent_reset_0 synchronousEdges DEASSERT
set_interface_property persistent_reset_0 ENABLED true
set_interface_property persistent_reset_0 EXPORT_OF ""
set_interface_property persistent_reset_0 PORT_NAME_MAP ""
set_interface_property persistent_reset_0 CMSIS_SVD_VARIABLES ""
set_interface_property persistent_reset_0 SVD_ADDRESS_GROUP ""
add_interface_port persistent_reset_0 preset0 reset Output 1
#
# connection point persistent_reset_1
#
add_interface persistent_reset_1 reset start
set_interface_property persistent_reset_1 associatedClock clock
set_interface_property persistent_reset_1 associatedDirectReset ""
set_interface_property persistent_reset_1 associatedResetSinks ""
set_interface_property persistent_reset_1 synchronousEdges DEASSERT
set_interface_property persistent_reset_1 ENABLED true
set_interface_property persistent_reset_1 EXPORT_OF ""
set_interface_property persistent_reset_1 PORT_NAME_MAP ""
set_interface_property persistent_reset_1 CMSIS_SVD_VARIABLES ""
set_interface_property persistent_reset_1 SVD_ADDRESS_GROUP ""
add_interface_port persistent_reset_1 preset1 reset Output 1