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kernel3_underclock.patch
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kernel3_underclock.patch
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diff --git a/arch/arm/mach-msm/acpuclock-7x30.c b/arch/arm/mach-msm/acpuclock-7x30.c
index 7ee4e5b..d190d98 100644
--- a/arch/arm/mach-msm/acpuclock-7x30.c
+++ b/arch/arm/mach-msm/acpuclock-7x30.c
@@ -112,14 +114,17 @@ static struct clk *acpuclk_sources[MAX_SOURCE];
* know all the h/w requirements.
*/
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
- { 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
- { 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
+ { 1, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
+ { 1, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
- { 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
- { 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
+ { 1, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
+ { 1, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
/* AXI has MSMC1 implications. See above. */
+ { 1, 460800, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
+ { 1, 576000, PLL_1, 2, 0, 153600000, 1000, VDD_RAW(1000) },
+ { 1, 652800, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
{ 1, 768000, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
/*
* AXI has MSMC1 implications. See above.