Describes the core memory interfaces used to fetch instructions and read/write data.
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The data and instruction interfaces use a simple "SRAM style" interface with stalling.
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Can be easily re-mapped to AXI/AMBA/BRAM etc.
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Easily attatches to caches.
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Bits | Driver | Name | Description |
---|---|---|---|
1 | Core | mem_req |
Memory request |
1 | Core | mem_rtype |
Request type: instruction / data. |
32 | Core | mem_addr |
Memory request address |
1 | Core | mem_wen |
Memory request write enable |
8 | Core | mem_strb |
Memory request write strobe |
64 | Core | mem_wdata |
Memory write data. |
2 | Core | mem_prv |
Privilidge level: 2=MMode,1=UMode. |
1 | Memory | mem_gnt |
Memory response valid |
1 | Memory | mem_err |
Memory response error |
64 | Memory | mem_rdata |
Memory response read data |
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A request is started by the core asserting
mem_req
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If
mem_gnt
is also asserted, then on the next cycle, the memory response will be recieved. -
If
mem_gnt
is not asserted, then the request signals must remain stable until it is.
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A new request can start when
mem_gnt
andmem_req
are both asserted.-
mem_err
andmem_rdata
can only be sampled the cycle after bothmem_gnt
andmem_req
are asserted. -
Core driven signals may change on the cycle where
mem_req
andmem_gnt
are high.
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