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Makefile.verilog
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Makefile.verilog
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#######################################
# Simulation run-time flags
MAX_CYCLES ?= 100000000
WAVE ?= 0
TRACE ?= 0
PC_HIST ?= 0
COVERAGE ?= 0
PROG_NAME ?= main
# Coverage Analysis
CM_NAME ?= $(notdir $(shell pwd))
COV_DIR ?= $(abspath ../coverage)
COV_DB_NAME ?= simv
########################################
# CAD Setup
ifneq ($(IGNORE_CADENV),)
$(info CAD Environment: Ignoring cadenv)
# select the tools
# Checking the VCS settings
else ifeq (,$findstring(cs.washington.edu,$(HOSTNAME)))
ifeq ($(VCS),)
$(error Unfamiliar machine/cadtool setup: Please define the $$VCS which points to the VCS binaries )
endif
ifeq ($(DVE),)
$(error Please define the $$DVE which points to the DVE binaries )
endif
# Using the cadenv.mk to setup the VCS
else
$(info CAD Environment: using $(CAD_DIR)/cadenv.mk to configure cad tools)
include $(CAD_DIR)/cadenv.mk
endif
#######################################
# Simulator setup
ifeq ($(BSG_PLATFORM),vcs)
BSG_SIM_BASE = simv
else ifeq ($(BSG_PLATFORM),verilator)
BSG_SIM_BASE = simsc
endif
ifeq ($(WAVE),0)
ifeq ($(PC_HIST),0)
ifeq ($(TRACE),0)
ifeq ($(COVERAGE),0)
BSG_SIM_EXE = $(BSG_MACHINE_PATH)/$(BSG_SIM_BASE)
else
BSG_SIM_EXE = $(BSG_MACHINE_PATH)/$(BSG_SIM_BASE)-coverage
endif
else
BSG_SIM_EXE = $(BSG_MACHINE_PATH)/$(BSG_SIM_BASE)-profile
endif
else
BSG_SIM_EXE = $(BSG_MACHINE_PATH)/$(BSG_SIM_BASE)-pc-histogram
endif
else
BSG_SIM_EXE = $(BSG_MACHINE_PATH)/$(BSG_SIM_BASE)-debug
endif
# Network boot format file
NBF_FILE = $(PROG_NAME).nbf
# Trace file is used for initialization / reset procedures
# Using trace file is optional
TRACE_FILE ?= $(BSG_MACHINE_PATH)/bsg_tag_boot.tr
BSG_SIM_OPTS = +nbf_file=$(NBF_FILE) \
+trace_file=$(TRACE_FILE) \
+max_cycle=$(MAX_CYCLES) \
+num_finish=$(NUM_FINISH) \
+vanilla_trace_en=$(TRACE) \
+coverage_en=$(COVERAGE) \
-licqueue -reportstats \
-l run.log
ifneq ($(COVERAGE), 0)
BSG_SIM_OPTS += -cm line+fsm+branch+cond+tgl -cm_name $(CM_NAME) -cm_dir $(COV_DIR)/$(COV_DB_NAME).vdb
endif
########################################
# Simulation Run Target
$(info Machine executable: $(BSG_SIM_EXE))
%.run: NBF_FILE=$*.nbf
%.run: %.nbf
# Rebuid the machine if machines dir is internal
ifeq ($(abspath $(BSG_MACHINE_PATH)/..),$(abspath $(BSG_MANYCORE_DIR)/machines))
$(MAKE) -C $(BSG_MACHINE_PATH)/.. $(BSG_SIM_EXE)
endif
$(BSG_SIM_EXE) $(BSG_SIM_OPTS)
ifeq ($(TRACE),1)
PYTHONPATH=$(BSG_MANYCORE_DIR)/software/py/vanilla_parser/.. python3 -m vanilla_parser --generate-key
endif
###################################################
# Need to move below to machines directory
#
##INC_OP = +incdir+
##
##VCS_OP = -full64 -sverilog +v2k
##VCS_OP += -timescale=1ps/1ps
##VCS_OP += -l vcs.log
##VCS_LINT = +lint=all,noSVA-UA,noSVA-NSVU,noVCDE,noNS
##
##VCS_OPTIONS = +define+SPMD=$*+
##VCS_OPTIONS += +define+bsg_hetero_type_vec="${bsg_hetero_type_vec}"+
##VCS_OPTIONS += +define+enable_vcache="${ENABLE_VCACHE}"
##VCS_RUN_OP =
##
##include $(BSG_MANYCORE_DIR)/software/mk/Makefile.verilog.loader
##
##ifeq ($(DVE),1)
##VCS_OP += +vcs+vcdpluson
##endif
##
##
######################################################
### VCS coverge options
##
##VCS_COV_COMP_OP =
##VCS_COV_RUN_OP =
##ifeq ($(COVERAGE),VCS)
##VCS_COV_COMP_OP += -cm_hier $(VCS_COV_HIER_CONFIG)
##VCS_COV_COMP_OP += -cm_dir $(PROG_NAME).vdb/
##VCS_COV_COMP_OP += -cm line+tgl
##VCS_COV_COMP_OP += -cm_line contassign
##VCS_COV_COMP_OP += -cm_noconst
##VCS_COV_COMP_OP += -cm_seqnoconst
###VCS_COV_COMP_OP += -cm_constfile $(VCS_COV_CONST_FILE)
##VCS_COV_COMP_OP += -diag noconst
##VCS_COV_COMP_OP += -cm_ignorepragmas
##VCS_COV_RUN_OP += -cm_dir $(PROG_NAME).vdb/
##VCS_COV_RUN_OP += -cm line+tgl
##endif
##
##VCS_OP += $(VCS_COV_COMP_OP)
##VCS_RUN_OP += $(VCS_COV_RUN_OP)