Peripheral Access Conventions

Worked Exmaples

        <peripheral>
            <name>AUDIO</name>
            <baseAddress>0xF0016000</baseAddress>
            <groupName>AUDIO</groupName>
            <registers>
                <register>
                    <name>RX_CTL</name>
                    <description><![CDATA[Rx data path control]]></description>
                    <addressOffset>0x000c</addressOffset>
                    <resetValue>0x00</resetValue>
                    <size>32</size>
                    <access>read-write</access>
                    <fields>
                        <field>
                            <name>enable</name>
                            <msb>0</msb>
                            <bitRange>[0:0]</bitRange>
                            <lsb>0</lsb>
                            <description><![CDATA[Enable the receiving data]]></description>
                        </field>
                        <field>
                            <name>reset</name>
                            <msb>1</msb>
                            <bitRange>[1:1]</bitRange>
                            <lsb>1</lsb>
                            <description><![CDATA[Writing `1` resets the FIFO. Reset happens regardless of enable state.]]></description>
                        </field>
                    </fields>
                </register>
            </registers>
         </peripheral>

csr_base,audio,0xf0016000,,
csr_register,audio_rx_ctl,0xf001600c,1,rw

    let audio_base = (HW_AUDIO_BASE as *mut u32) as *mut Volatile<u32>;

    let rx_ctl = (*audio_base.add(HW_AUDIO_RX_CTL)).r();

    (*audio_base.add(HW_AUDIO_RX_CTL)).ow(HW_AUDIO_RX_CTL_RESET);
    (*audio_base.add(HW_AUDIO_RX_CTL)).ow(1, HW_AUDIO_RX_CTL_RESET_MASK, HW_AUDIO_RX_CTL_RESET_OFFSET);
    (*audio_base.add(HW_AUDIO_RX_CTL)).ow(False, HW_AUDIO_RX_CTL_RESET_MASK);

    (*audio_base.add(HW_AUDIO_RX_CTL))
       .rw(False, HW_AUDIO_RX_CTL_RESET_MASK, HW_AUDIO_RX_CTL_RESET_OFFSET)
       .rw(True, HW_AUDIO_RX_CTL_ENABLE_MASK, HW_AUDIO_RX_CTL_ENABLE_OFFSET);

```xml UART 0xF0004000 UART RXTX 0x0000 0x00 32 read-write rxtx 7 [7:0] 0 ``` ```csv csr_base,uart,0xf0004000,, csr_register,uart_rxtx,0xf0004000,1,rw ``` ```rust let uart_base = (HW_UART_BASE as *mut u32) as *mut Volatile;

let rx_char: u8 = (*uart_base.add(HW_UART_RXTX)).r() as u8;

(*uart_base.add(HW_UART_RXTX)).ow(tx_char, HW_UART_RXTX_MASK, HW_UART_RXTX_OFFSET);

(*uart_base.add(HW_UART_RXTX))
   .rw(tx_char, HW_UART_RXTX_MASK, HW_UART_RXTX_OFFSET)