generated from MiSTer-devel/Template_MiSTer
-
Notifications
You must be signed in to change notification settings - Fork 1
/
files.qip
48 lines (44 loc) · 2.8 KB
/
files.qip
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
# MiSTer-specific
set_global_assignment -name SDC_FILE Nand2Tetris.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Nand2Tetris.sv
# Hack Computer
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Nand2Tetris_top.sv
set_global_assignment -name VERILOG_FILE rtl/structural/ALU.v
# Elementary Logic Gates
set_global_assignment -name VERILOG_FILE rtl/structural/gates/AND.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/BUFFER.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/NAND.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/NOR.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/NOT.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/OR.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/XNOR.v
set_global_assignment -name VERILOG_FILE rtl/structural/gates/XOR.v
# Composite Logic Chips
set_global_assignment -name VERILOG_FILE rtl/structural/chips/2to4Dec.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/4to2Enc.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Add16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/And16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Bit.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/DFF.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Dmux.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Dmux4Way.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Dmux8Way.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/FullAdder.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/HalfAdder.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Inc16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Mux.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Mux16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Mux4Way16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Mux8Way16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Not16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Or8Way.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Or16.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/PC.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/RAM16K.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/RAM4K.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/RAM8.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/RAM64.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/RAM512.v
set_global_assignment -name VERILOG_FILE rtl/structural/chips/Register.v
# Behavioral Modules (unused currently)
#set_global_assignment -name SYSTEMVERILOG_FILE rtl/ALU.sv