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Cortex M55/adiv6 support #1970
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Following on from the discussion, could we please have you re-run your JTAG scan with a higher verbosity level - 8 only turns on PROTO diagnostics which isn't especially useful here unfortunately. For this we're going to need INFO + TARGET + PROBE, which is (1 + 4 + 16) or in other words, 21 for |
There you go
The SWD scan fails as well unfortunately
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Ack, the SWD side might well need #1959 to work then if this part implements dormant state. We'll try and get that PR reviewed today to check it's inserting a fully correct JTAG -> DS sequence and that it runs through the JTAG-or-SWD state machine correctly. With regards to the JTAG side of this, that didn't produce as much output as we were expecting, so could you please crank the debug output further to |
Next try ;) blackmagic -tjv 45
I'll give #1959 a try tomorrow as well. Thanks, I really appreciate the effort! |
Thank you very much! We'll dig into the logs in a bit and go decoding |
Okay, so - it turns out that we were correct to think there would need to be some low-level changes for ADIv6 JTAG - they split out the OK/FAULT codes for the ACK and BMD is interpreting the OK ACK code as an invalid ACK here. Hence E104 which is indicating the firmware threw an exception in response. A fix for that is now available on feature/adiv6-jtag-support though we are certain that branch will not work correctly yet as we didn't yet get past the low-level aspects. Hopefully it get significantly further though. You will need to upgrade your probe's firmware for this to work. |
Here are the logs from feature/adiv6-jtag-support, looks quite the same unfortunately. build/blackmagic -tjv45
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Interesting.. given that's still using the high-level API to drive what it's doing, could we please ask you to pass Edit: Turns out that in trying to correct the missing ACK handling, we broke a core part of |
Next try ./build/blackmagic -Htjv 45
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Thank you for the update and re-try - there's something really odd going on here which looks like it's going to take some additional debugging to figure out. If we decode the DPIDR request-response cycle, we get this as the result:
DPIDR should be reading something more like 0x4ba03477 for this part, not 0x00000004. That ack value of 0 is also very off Edit: Ah, part of the PDIDR read routine assumes SWD right now, which means the RDBUFF read to actually get the response to the request is never done.. fixing that too. |
We have just pushed a couple of changes to the branch that follow up on SELECT's value being questionable before the read, and the DPIDR read assuming SWD. We've tested it as best we can on the parts we have here, and it appears like it is working better (LPC4370 has a couple of JTAG-DP's that have IDCode 0x0ba01477 and when we remove the errata workaround for those, their DPIDR's read out a semi-sensical value of 0x0bb11477 now which is considerably better behaviour than before). |
Now we're getting somewhere, output is to large to paste as text ;) |
Given that got us so much further, you'd be welcome to drop the Please could we get Edit: As a side note, we're pleased to see that the ADIv6 environment once DPIDR has been read looks the same under JTAG as under SWD, that is a huge relief with how complicated things would have been otherwise. The next real hurdle is component identification and figuring out what, eg, a component PIDR of |
🙃 with -H it produces more output Edit: From what I can tell from the datasheets it should be "compliant with the Arm® Debug Interface Architecture Specification ADIv6.0" and there is talk about "CoreSight (CS) ROM". Sorry for being cryptic, I'll try to (get permission to) share more information ;) |
Oh, interesting that the remote protocol flumps like that - having the output of Yes, this device is complaint with ADIv6, that's why we've been having to do what we have to make it work, however that doesn't explain the base DP debug resource bus ROM table contents - specifically the PIDRs for the resources it defines seemingly not being anything we can find in the TRMs. That said, if that first resource is a ROM and noting that the SoC-600 TRM leaves the PIDR value for a ROM intentionally undefined, that could explain that: Edit: However, the lack of DEVARCH non-zero value is a problem for that theory as that's the way you're supposed to tell it's one of those ROM tables. As mentioned, that PIDR doesn't appear anywhere in the CoreSight SoC-600 TRM, so any information you are able to get permission to share about the DP's ROM table specifically, would be greatly helpful. Once we can locate the Cortex-M55 core itself, we can use the Cortex-M55 TRM to help identify components that are not already identified. |
We have updated the branch to include as many of the previously unknown CoreSight components as we were able to identify from the ROM tables and the CoreSight SoC-600 TRM + Cortex-M55 TRM. We have added the Cortex-M55 CPUID to the known CPUIDs and translated it. This should get things much further, but will still leave large gaps of "Debug component - Unknown" in the ROM tables display. |
blackmagic -tjv 45
The details are behind NDAs unfortunately 🤐 The chip has 2 M55 cores if that helps. |
Thank you for the debug log from the remote protocol - very curious that writing SELECT explodes like that, but this gives us plenty of detail to work from to figure out why and how. Thank you. We're extremely surprised that the ARM-made debug components on the DP are being held under NDA too - we understand if the Vendor doesn't want to share details of their components at this time, but the components that have us eyebrow raised have PIDRs |
Thanks for all the help! It's not necessarily the debug components themselves, but the architecture of the chip, i.e. I'd have to cite a document that is under an NDA. |
Ahh, we see - and we're guessing you don't necessarily know which ARM document defines the debug components in question to cite instead.. what a pickle. Still, we got most of the debug components figured out as they're defined in either the CoreSight SoC-600 TRM or the Cortex-M55 TRM, so you should see good decodes of most of the ROM tables now and BMD should see the Cortex-M55 cores and make them available as targets now. We'll update this issue if we figure out what's going on with the remote protocol there and potentially a bugfix for it. |
Okidokie, so - the remote protocol issue comes around because the protocol does not currently convey the DP version with the request packets, resulting in the firmware thinking the DP is a DPv0 while BMDA thinks it's a DPv3 and necessarily resulting in the ACK codes being mishandled in adiv5_jtag.c and an exception being thrown due to bad ACK (E104 -> Error, exception thrown, exception kind 1 aka We will go away and think on how on earth to make the infrastructure for JTAG work properly to avoid this problem and will update the issue again when we have something for you to test. |
Please give the latest version of the branch a try, which implements a DP version command in the ADIv5 acceleration remote protocol. This should solve the remote protocol crash. |
Sweet, |
That is a huge relief to hear! We'll get that branch converted to a PR then so it can be merged to |
I don't know if it is related (I'm more assuming some issue with how I setup the chip), but while Do you know if this could be somehow related to the debugger? |
There is a chance, especially as we did not yet look at the Cortex-M55's DWT or FPB, that the control of those units for those debug functions is not quite right for the M55 and so causing that to occur - from memory, cortexm.c presumes one of two FPB unit versions, and if the new cores use a new version, adjustments likely need to be made. |
As a note about the closure on this issue: We'll address the core-specific issues separately with a follow-up PR diving into what could be going wrong with the debugging the core. That keeps the PRs from getting out of hand and having too broad a scope. We hope you'll be willing to test whatever changes wind up being required to make debug on the core work, seeing we don't have any Cortex-M55 targets here right now to be able to test changes against. We'll work from the TRMs and write changes based on the theory of what we're seeing, but this obviously doesn't always match up with reality. |
Of course! I'm happy to help (and benefit from having a nice debugger ;)). Please just tag me on related PRs |
We have just opened #2010 which between it and #2008 addresses what we could reproduce of the Cortex-M55 debug issue. Please let us know how you get on with these two PRs and what remains of the problems you were seeing. mean00's PR should fully address the DWT issues as ARMv8-M defines a new DWT which is why BMD was miss-driving it. |
Discussed in #1969
Originally posted by florg-32 October 18, 2024
Hey guys,
I have a Cortex M55 chip I'd like to debug with my BMP. Should this be supported already (on nightly builds)?
My gdb
monitor jtag_scan
does not find the device, voltage is detected correctly though and resetting works. The debug app outputs the following, which I don't really understand; shouldn't it be ADIv6?Thanks,
Florian
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