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xcore.SPEC
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xcore.SPEC
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****************
Platform: XCore
Code:0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 0x09 0xfd 0xec 0xa7
Disasm:
0x1000: get r11, ed
op_count: 2
operands[0].type: REG = r11
operands[1].type: REG = ed
0x1002: ldw et, sp[4]
op_count: 2
operands[0].type: REG = et
operands[1].type: MEM
operands[1].mem.base: REG = sp
operands[1].mem.disp: 0x4
0x1004: setd res[r3], r4
op_count: 1
operands[0].type: REG = r4
0x1006: init t[r2]:lr, r1
op_count: 2
operands[0].type: MEM
operands[0].mem.base: REG = r2
operands[0].mem.index: REG = lr
operands[1].type: REG = r1
0x100a: divu r9, r1, r3
op_count: 3
operands[0].type: REG = r9
operands[1].type: REG = r1
operands[2].type: REG = r3
0x100e: lda16 r9, r3[-r11]
op_count: 1
operands[0].type: REG = r9
0x1012: ldw dp, dp[0x81c5]
op_count: 1
operands[0].type: REG = dp
0x1016: lmul r11, r0, r2, r5, r8, r10
op_count: 6
operands[0].type: REG = r11
operands[1].type: REG = r0
operands[2].type: REG = r2
operands[3].type: REG = r5
operands[4].type: REG = r8
operands[5].type: REG = r10
0x101a: add r1, r2, r3
op_count: 3
operands[0].type: REG = r1
operands[1].type: REG = r2
operands[2].type: REG = r3
0x101c: ldaw r8, r2[-9]
op_count: 1
operands[0].type: REG = r8
0x1020: