Bus negation problem

[Sei-Lisa]

Not sure if this is the best place to report problems.

I'm having a problem with 2.0-b10:

The outputs should be the same, but the negated input of the top gate is not applied bitwise.

[bnoordhuis]

Can you post or upload a small sample file that demonstrates the issue? The more minimal, the better.

[Sei-Lisa]

Issue 5 test case

I made the above example as a minimal test case to demonstrate wrong behaviour (top display) and correct behaviour (bottom display). It happens with any gate with buses as input, when negating an input. The negated input results in a value of zero, instead of the bitwise not of the input value. If it is an OR or XOR gate, the value is the one in the other input, regardless of the value in the negated input. If it is an AND gate, as above, the output is always zero.

This was working as expected in older versions, because I detected it when loading an old diagram that was working.

[Sei-Lisa]

This patch fixes it for me:

--- a/src/tkgate/and.c	2020-08-18 00:59:55.055110382 +0200
+++ b/src/tkgate/and.c	2020-08-18 01:00:36.978226845 +0200
@@ -329,7 +329,7 @@
       first_pin = 0;
 
       if (gi->Pad[i].iotype == IN && w->invert)
-	inv = "!";
+	inv = "~";
 
       if (gi->Pad[i].CanAdd)
 	fprintf(f,".%s%d",gi->Pad[i].Name,j);

I can't tell if this may have other side effects, but it doesn't seem logical that inverting a bus wire behaves as logic NOT instead of bitwise NOT.