LAB3 spec Puzzle #118
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kevin861222
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以目前我對bram的瞭解,如果要對bram進行reset,會需要自己幫他們做reset,因此會需要花多個cycle,原因也正如你所說bram沒有reset port。 |
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Yes, the state machine should have a state, say "INIT" to initialize the internal states, including the SRAM content, status, ... |
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請問lab3 中 fir 發生axi_reset_n的負緣觸發時,需要reset兩個bram的資料嗎?
通常asic中的bram沒有reset port,這樣是不是意味著要花上11或12個cycle才能完成reset呢?
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