Some questions about Vitis analyzer and OpenCL host code

[s095339]

Hi, I have 2 question about XRT platform
Does the "Data Transfer" that I specified with a red rectangle means "transfering buffers(or data) from host to FPGA" ?

If so, I wonder that if the host starts transfer data after the host function "clEnqueueMigrateMemobjects()" being called or not.
The reason why I ask this question is because I found that the parallel write operation starts after "clEnqueueTast()" being called.