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lower.isle
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lower.isle
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;; aarch64 instruction selection and CLIF-to-MachInst lowering.
;; The main lowering constructor term: takes a clif `Inst` and returns the
;; register(s) within which the lowered instruction's result values live.
(decl partial lower (Inst) InstOutput)
;; Variant of the main lowering constructor term, which receives an
;; additional argument (a vector of branch targets to be used) for
;; implementing branches.
;; For two-branch instructions, the first target is `taken` and the second
;; `not_taken`, even if it is a Fallthrough instruction: because we reorder
;; blocks while we lower, the fallthrough in the new order is not (necessarily)
;; the same as the fallthrough in CLIF. So, we use the explicitly-provided
;; target.
(decl partial lower_branch (Inst MachLabelSlice) Unit)
;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
(imm ty (ImmExtend.Zero) n))
;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (null)))
(imm ty (ImmExtend.Zero) 0))
;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (f32const (u32_from_ieee32 n)))
(constant_f32 n))
;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (f64const (u64_from_ieee64 n)))
(constant_f64 n))
;;;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (nop))
(invalid_reg))
;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller
;; Base case, simply adding things in registers.
(rule -1 (lower (has_type (fits_in_64 ty) (iadd x y)))
(add ty x y))
;; Special cases for when one operand is an immediate that fits in 12 bits.
(rule 4 (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
(add_imm ty x y))
(rule 5 (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
(add_imm ty y x))
;; Same as the previous special cases, except we can switch the addition to a
;; subtraction if the negated immediate fits in 12 bits.
(rule 2 (lower (has_type (fits_in_64 ty) (iadd x y)))
(if-let imm12_neg (imm12_from_negated_value y))
(sub_imm ty x imm12_neg))
(rule 3 (lower (has_type (fits_in_64 ty) (iadd x y)))
(if-let imm12_neg (imm12_from_negated_value x))
(sub_imm ty y imm12_neg))
;; Special cases for when we're adding an extended register where the extending
;; operation can get folded into the add itself.
(rule 0 (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
(add_extend ty x y))
(rule 1 (lower (has_type (fits_in_64 ty) (iadd (extended_value_from_value x) y)))
(add_extend ty y x))
;; Special cases for when we're adding the shift of a different
;; register by a constant amount and the shift can get folded into the add.
(rule 7 (lower (has_type (fits_in_64 ty)
(iadd x (ishl y (iconst k)))))
(if-let amt (lshl_from_imm64 ty k))
(add_shift ty x y amt))
(rule 6 (lower (has_type (fits_in_64 ty)
(iadd (ishl x (iconst k)) y)))
(if-let amt (lshl_from_imm64 ty k))
(add_shift ty y x amt))
;; Fold an `iadd` and `imul` combination into a `madd` instruction.
(rule 7 (lower (has_type (fits_in_64 ty) (iadd x (imul y z))))
(madd ty y z x))
(rule 6 (lower (has_type (fits_in_64 ty) (iadd (imul x y) z)))
(madd ty x y z))
;; Fold an `isub` and `imul` combination into a `msub` instruction.
(rule (lower (has_type (fits_in_64 ty) (isub x (imul y z))))
(msub ty y z x))
;; vectors
(rule -2 (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
(add_vec x y (vector_size ty)))
;; `i128`
(rule -3 (lower (has_type $I128 (iadd x y)))
(let
;; Get the high/low registers for `x`.
((x_regs ValueRegs x)
(x_lo Reg (value_regs_get x_regs 0))
(x_hi Reg (value_regs_get x_regs 1))
;; Get the high/low registers for `y`.
(y_regs ValueRegs y)
(y_lo Reg (value_regs_get y_regs 0))
(y_hi Reg (value_regs_get y_regs 1)))
;; the actual addition is `adds` followed by `adc` which comprises the
;; low/high bits of the result
(with_flags
(add_with_flags_paired $I64 x_lo y_lo)
(adc_paired $I64 x_hi y_hi))))
;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; When a single element of one vector is broadcast to all the destination
;; lanes then the `dup` instruction can be used for this operation. Note that
;; for now this only matches lane selection from the first vector `a`, but
;; if necessary in the future rules can be added to select from `b` as well.
(rule 6 (lower (shuffle a b (shuffle_dup8_from_imm n)))
(vec_dup_from_fpu a (VectorSize.Size8x16) n))
(rule 5 (lower (shuffle a b (shuffle_dup16_from_imm n)))
(vec_dup_from_fpu a (VectorSize.Size16x8) n))
(rule 4 (lower (shuffle a b (shuffle_dup32_from_imm n)))
(vec_dup_from_fpu a (VectorSize.Size32x4) n))
(rule 3 (lower (shuffle a b (shuffle_dup64_from_imm n)))
(vec_dup_from_fpu a (VectorSize.Size64x2) n))
;; If the `Immediate` specified to the extractor looks like a duplication of the
;; `n`th lane of the first vector of size K-byte lanes, then each extractor
;; returns the `n` value as a `u8` to be used as part of a `vec_dup_from_fpu`
;; instruction. Note that there's a different extractor for each bit-width of
;; lane.
(decl shuffle_dup8_from_imm (u8) Immediate)
(extern extractor shuffle_dup8_from_imm shuffle_dup8_from_imm)
(decl shuffle_dup16_from_imm (u8) Immediate)
(extern extractor shuffle_dup16_from_imm shuffle_dup16_from_imm)
(decl shuffle_dup32_from_imm (u8) Immediate)
(extern extractor shuffle_dup32_from_imm shuffle_dup32_from_imm)
(decl shuffle_dup64_from_imm (u8) Immediate)
(extern extractor shuffle_dup64_from_imm shuffle_dup64_from_imm)
;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
;; bytes", that's an `ext` instruction.
(rule 2 (lower (shuffle a b (vec_extract_imm4_from_immediate n)))
(vec_extract a b n))
;; Attempts to extract `n` from the specified shuffle `Immediate` where each
;; byte of the `Immediate` is a consecutive sequence starting from `n`. This
;; value of `n` is used as part of the `vec_extract` instruction which extracts
;; consecutive bytes from two vectors into one final vector, offset by `n`
;; bytes.
(decl vec_extract_imm4_from_immediate (u8) Immediate)
(extern extractor vec_extract_imm4_from_immediate vec_extract_imm4_from_immediate)
;; Rules for the `uzp1` and `uzp2` instructions which gather even-numbered lanes
;; or odd-numbered lanes
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1e1c_1a18_1614_1210_0e0c_0a08_0604_0200)))
(vec_uzp1 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1d_1b19_1715_1311_0f0d_0b09_0705_0301)))
(vec_uzp2 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1d1c_1918_1514_1110_0d0c_0908_0504_0100)))
(vec_uzp1 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_1b1a_1716_1312_0f0e_0b0a_0706_0302)))
(vec_uzp2 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1b1a1918_13121110_0b0a0908_03020100)))
(vec_uzp1 a b (VectorSize.Size32x4)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_17161514_0f0e0d0c_07060504)))
(vec_uzp2 a b (VectorSize.Size32x4)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1716151413121110_0706050403020100)))
(vec_uzp1 a b (VectorSize.Size64x2)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c1b1a1918_0f0e0d0c0b0a0908)))
(vec_uzp2 a b (VectorSize.Size64x2)))
;; Rules for the `zip1` and `zip2` instructions which interleave lanes in the
;; low or high halves of the two input vectors.
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1707_1606_1505_1404_1303_1202_1101_1000)))
(vec_zip1 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f0f_1e0e_1d0d_1c0c_1b0b_1a0a_1909_1808)))
(vec_zip2 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1716_0706_1514_0504_1312_0302_1110_0100)))
(vec_zip1 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1d1c_0d0c_1b1a_0b0a_1918_0908)))
(vec_zip2 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x17161514_07060504_13121110_03020100)))
(vec_zip1 a b (VectorSize.Size32x4)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_1b1a1918_0b0a0908)))
(vec_zip2 a b (VectorSize.Size32x4)))
;; Note that zip1/zip2 for i64x2 vectors is omitted since it's already covered
;; by the i64x2 cases of uzp1/uzp2 above where both zip and uzp have the same
;; semantics for 64-bit lanes.
;; Rules for the `trn1` and `trn2` instructions which interleave odd or even
;; lanes in the two input vectors.
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1e0e_1c0c_1a0a_1808_1606_1404_1202_1000)))
(vec_trn1 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f0f_1d0d_1b0b_1909_1707_1505_1303_1101)))
(vec_trn2 a b (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1d1c_0d0c_1918_0908_1514_0504_1110_0100)))
(vec_trn1 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1b1a_0b0a_1716_0706_1312_0302)))
(vec_trn2 a b (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1b1a1918_0b0a0908_13121110_03020100)))
(vec_trn1 a b (VectorSize.Size32x4)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_17161514_07060504)))
(vec_trn2 a b (VectorSize.Size32x4)))
;; Note that trn1/trn2 for i64x2 vectors is omitted since it's already covered
;; by the i64x2 cases of uzp1/uzp2 above where both trn and uzp have the same
;; semantics for 64-bit lanes.
;; Rules for the `rev{16,32,64}` instructions where reversals happen at either
;; the byte level, the 16-bit level, or 32-bit level. Note that all of these
;; patterns only match reversals in the first operand, but they can
;; theoretically be extended if necessary to reversals in the second operand.
(rule 1 (lower (shuffle a b (u128_from_immediate 0x0e0f_0c0d_0a0b_0809_0607_0405_0203_0001)))
(rev16 a (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x0c0d0e0f_08090a0b_04050607_00010203)))
(rev32 a (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x0d0c0f0e_09080b0a_05040706_01000302)))
(rev32 a (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x08090a0b0c0d0e0f_0001020304050607)))
(rev64 a (VectorSize.Size8x16)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x09080b0a0d0c0f0e_0100030205040706)))
(rev64 a (VectorSize.Size16x8)))
(rule 1 (lower (shuffle a b (u128_from_immediate 0x0b0a09080f0e0d0c_0302010007060504)))
(rev64 a (VectorSize.Size32x4)))
(rule (lower (has_type ty (shuffle rn rn2 (u128_from_immediate mask))))
(let ((mask_reg Reg (constant_f128 mask)))
(vec_tbl2 rn rn2 mask_reg ty)))
;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type vec_i128_ty (swizzle rn rm)))
(vec_tbl rn rm))
;;;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (isplit x @ (value_type $I128)))
(let
((x_regs ValueRegs x)
(x_lo ValueRegs (value_regs_get x_regs 0))
(x_hi ValueRegs (value_regs_get x_regs 1)))
(output_pair x_lo x_hi)))
;;;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $I128 (iconcat lo hi)))
(output (value_regs lo hi)))
;;;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F32X4 (scalar_to_vector x)))
(fpu_extend x (ScalarSize.Size32)))
(rule (lower (has_type $F64X2 (scalar_to_vector x)))
(fpu_extend x (ScalarSize.Size64)))
(rule -1 (lower (scalar_to_vector x @ (value_type $I64)))
(mov_to_fpu x (ScalarSize.Size64)))
(rule -2 (lower (scalar_to_vector x @ (value_type (int_fits_in_32 _))))
(mov_to_fpu (put_in_reg_zext32 x) (ScalarSize.Size32)))
;;;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; cmeq vtmp.2d, vm.2d, #0
;; addp dtmp, vtmp.2d
;; fcmp dtmp, dtmp
;; cset xd, eq
;;
;; Note that after the ADDP the value of the temporary register will be either
;; 0 when all input elements are true, i.e. non-zero, or a NaN otherwise
;; (either -1 or -2 when represented as an integer); NaNs are the only
;; floating-point numbers that compare unequal to themselves.
(rule (lower (vall_true x @ (value_type (multi_lane 64 2))))
(let ((x1 Reg (cmeq0 x (VectorSize.Size64x2)))
(x2 Reg (addp x1 x1 (VectorSize.Size64x2))))
(with_flags (fpu_cmp (ScalarSize.Size64) x2 x2)
(materialize_bool_result (Cond.Eq)))))
(rule (lower (vall_true x @ (value_type (multi_lane 32 2))))
(let ((x1 Reg (mov_from_vec x 0 (ScalarSize.Size64))))
(with_flags (cmp_rr_shift (OperandSize.Size64) (zero_reg) x1 32)
(ccmp_imm
(OperandSize.Size32)
x1
(u8_into_uimm5 0)
(nzcv $false $true $false $false)
(Cond.Ne)))))
;; This operation is implemented by using uminv to create a scalar value, which
;; is then compared against zero.
;;
;; uminv bn, vm.16b
;; mov xm, vn.d[0]
;; cmp xm, #0
;; cset xm, ne
(rule -1 (lower (vall_true x @ (value_type (lane_fits_in_32 ty))))
(if (not_vec32x2 ty))
(let ((x1 Reg (vec_lanes (VecLanesOp.Uminv) x (vector_size ty)))
(x2 Reg (mov_from_vec x1 0 (ScalarSize.Size64))))
(with_flags (cmp_imm (OperandSize.Size64) x2 (u8_into_imm12 0))
(materialize_bool_result (Cond.Ne)))))
;;;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (vany_true x @ (value_type in_ty)))
(with_flags (vanytrue x in_ty)
(materialize_bool_result (Cond.Ne))))
;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; special case for the `i16x8.extadd_pairwise_i8x16_s` wasm instruction
(rule (lower (has_type $I16X8 (iadd_pairwise (swiden_low x) (swiden_high x))))
(saddlp8 x))
;; special case for the `i32x4.extadd_pairwise_i16x8_s` wasm instruction
(rule (lower (has_type $I32X4 (iadd_pairwise (swiden_low x) (swiden_high x))))
(saddlp16 x))
;; special case for the `i16x8.extadd_pairwise_i8x16_u` wasm instruction
(rule (lower (has_type $I16X8 (iadd_pairwise (uwiden_low x) (uwiden_high x))))
(uaddlp8 x))
;; special case for the `i32x4.extadd_pairwise_i16x8_u` wasm instruction
(rule (lower (has_type $I32X4 (iadd_pairwise (uwiden_low x) (uwiden_high x))))
(uaddlp16 x))
(rule -1 (lower (has_type ty (iadd_pairwise x y)))
(addp x y (vector_size ty)))
;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (iabs x)))
(vec_abs x (vector_size ty)))
(rule 2 (lower (has_type $I64 (iabs x)))
(abs (OperandSize.Size64) x))
(rule 1 (lower (has_type (fits_in_32 ty) (iabs x)))
(abs (OperandSize.Size32) (put_in_reg_sext32 x)))
; `rustc` implementation.
; - create a bitmask of all 1s if negative, or 0s if positive.
; - xor all bits by bitmask. then subtract bitmask from xor'd values.
; - if `x` is positive, the xor'd bits = x and the mask = 0, so we end up with
; `x - 0`.
; - if `x` is negative, the xor'd bits = ~x and the mask = -1, so we end up with
; `~x - (-1) = ~x + 1`, which is exactly `abs(x)`.
(rule (lower (has_type $I128 (iabs x)))
(let ((x_regs ValueRegs x)
(x_lo Reg (value_regs_get x_regs 0))
(x_hi Reg (value_regs_get x_regs 1))
(asr_reg Reg (asr_imm $I64 x_hi (imm_shift_from_u8 63)))
(eor_hi Reg (eor $I64 x_hi asr_reg))
(eor_lo Reg (eor $I64 x_lo asr_reg))
(subs_lo ProducesFlags (sub_with_flags_paired $I64 eor_lo asr_reg))
(sbc_hi ConsumesFlags (sbc_paired $I64 eor_hi asr_reg)))
(with_flags subs_lo sbc_hi)))
;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $I64X2 (avg_round x y)))
(let ((one Reg (splat_const 1 (VectorSize.Size64x2)))
(c Reg (orr_vec x y (VectorSize.Size64x2)))
(c Reg (and_vec c one (VectorSize.Size64x2)))
(x Reg (ushr_vec_imm x 1 (VectorSize.Size64x2)))
(y Reg (ushr_vec_imm y 1 (VectorSize.Size64x2)))
(sum Reg (add_vec x y (VectorSize.Size64x2))))
(add_vec c sum (VectorSize.Size64x2))))
(rule -1 (lower (has_type (lane_fits_in_32 ty) (avg_round x y)))
(vec_rrr (VecALUOp.Urhadd) x y (vector_size ty)))
;;;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (multi_lane _ _) (sqmul_round_sat x y)))
(vec_rrr (VecALUOp.Sqrdmulh) x y (vector_size ty)))
;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fadd rn rm)))
(vec_rrr (VecALUOp.Fadd) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fadd rn rm)))
(fpu_rrr (FPUOp2.Add) rn rm (scalar_size ty)))
;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fsub rn rm)))
(vec_rrr (VecALUOp.Fsub) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fsub rn rm)))
(fpu_rrr (FPUOp2.Sub) rn rm (scalar_size ty)))
;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fmul rn rm)))
(vec_rrr (VecALUOp.Fmul) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fmul rn rm)))
(fpu_rrr (FPUOp2.Mul) rn rm (scalar_size ty)))
;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fdiv rn rm)))
(vec_rrr (VecALUOp.Fdiv) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fdiv rn rm)))
(fpu_rrr (FPUOp2.Div) rn rm (scalar_size ty)))
;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fmin rn rm)))
(vec_rrr (VecALUOp.Fmin) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fmin rn rm)))
(fpu_rrr (FPUOp2.Min) rn rm (scalar_size ty)))
;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fmax rn rm)))
(vec_rrr (VecALUOp.Fmax) rn rm (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fmax rn rm)))
(fpu_rrr (FPUOp2.Max) rn rm (scalar_size ty)))
;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (sqrt x)))
(vec_misc (VecMisc2.Fsqrt) x (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (sqrt x)))
(fpu_rr (FPUOp1.Sqrt) x (scalar_size ty)))
;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fneg x)))
(vec_misc (VecMisc2.Fneg) x (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fneg x)))
(fpu_rr (FPUOp1.Neg) x (scalar_size ty)))
;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (fabs x)))
(vec_misc (VecMisc2.Fabs) x (vector_size ty)))
(rule (lower (has_type (ty_scalar_float ty) (fabs x)))
(fpu_rr (FPUOp1.Abs) x (scalar_size ty)))
;;;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F64 (fpromote x)))
(fpu_rr (FPUOp1.Cvt32To64) x (ScalarSize.Size32)))
;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F32 (fdemote x)))
(fpu_rr (FPUOp1.Cvt64To32) x (ScalarSize.Size64)))
;;;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (ceil x)))
(vec_misc (VecMisc2.Frintp) x (vector_size ty)))
(rule (lower (has_type $F32 (ceil x)))
(fpu_round (FpuRoundMode.Plus32) x))
(rule (lower (has_type $F64 (ceil x)))
(fpu_round (FpuRoundMode.Plus64) x))
;;;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (floor x)))
(vec_misc (VecMisc2.Frintm) x (vector_size ty)))
(rule (lower (has_type $F32 (floor x)))
(fpu_round (FpuRoundMode.Minus32) x))
(rule (lower (has_type $F64 (floor x)))
(fpu_round (FpuRoundMode.Minus64) x))
;;;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (trunc x)))
(vec_misc (VecMisc2.Frintz) x (vector_size ty)))
(rule (lower (has_type $F32 (trunc x)))
(fpu_round (FpuRoundMode.Zero32) x))
(rule (lower (has_type $F64 (trunc x)))
(fpu_round (FpuRoundMode.Zero64) x))
;;;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane _ _) (nearest x)))
(vec_misc (VecMisc2.Frintn) x (vector_size ty)))
(rule (lower (has_type $F32 (nearest x)))
(fpu_round (FpuRoundMode.Nearest32) x))
(rule (lower (has_type $F64 (nearest x)))
(fpu_round (FpuRoundMode.Nearest64) x))
;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(type IsFneg (enum (Result (negate u64) (value Value))))
(decl pure is_fneg (Value) IsFneg)
(rule 1 (is_fneg (fneg n)) (IsFneg.Result 1 n))
(rule 0 (is_fneg n) (IsFneg.Result 0 n))
(decl pure is_fneg_neg (IsFneg) u64)
(rule (is_fneg_neg (IsFneg.Result n _)) n)
(decl pure get_fneg_value (IsFneg) Value)
(rule (get_fneg_value (IsFneg.Result _ v)) v)
(decl fmadd_series (Type u64 Value Value Value) InstOutput)
(rule 0 (fmadd_series (ty_scalar_float ty) 0 x y z) (fpu_rrrr (FPUOp3.MAdd) (scalar_size ty) x y z))
(rule 0 (fmadd_series (ty_scalar_float ty) 1 x y z) (fpu_rrrr (FPUOp3.MSub) (scalar_size ty) x y z))
(rule (lower (has_type (ty_scalar_float ty) (fma x_src y_src z)))
(let
((x_res IsFneg (is_fneg x_src))
(y_res IsFneg (is_fneg y_src)))
(fmadd_series ty (u64_xor (is_fneg_neg x_res) (is_fneg_neg y_res)) (get_fneg_value x_res) (get_fneg_value y_res) z)))
;; Delegate vector-based lowerings to helpers below
(rule 1 (lower (has_type ty @ (multi_lane _ _) (fma x y z)))
(lower_fmla (VecALUModOp.Fmla) x y z (vector_size ty)))
;; Lowers a fused-multiply-add operation handling various forms of the
;; instruction to get maximal coverage of what's available on AArch64.
(decl lower_fmla (VecALUModOp Value Value Value VectorSize) Reg)
;; Base case, emit the op requested.
(rule (lower_fmla op x y z size)
(vec_rrr_mod op z x y size))
;; Special case: if one of the multiplicands are a splat then the element-based
;; fma can be used instead with 0 as the element index.
(rule 1 (lower_fmla op (splat x) y z size)
(vec_fmla_elem op z y x size 0))
(rule 2 (lower_fmla op x (splat y) z size)
(vec_fmla_elem op z x y size 0))
;; Special case: if one of the multiplicands is a shuffle to broadcast a
;; single element of a vector then the element-based fma can be used like splat
;; above.
;;
;; Note that in Cranelift shuffle always has i8x16 inputs and outputs so
;; a `bitcast` is matched here explicitly since that's the main way a shuffle
;; output will be fed into this instruction.
(rule 3 (lower_fmla op (bitcast _ (shuffle x x (shuffle32_from_imm n n n n))) y z size @ (VectorSize.Size32x4))
(if-let $true (u64_lt n 4))
(vec_fmla_elem op z y x size n))
(rule 4 (lower_fmla op x (bitcast _ (shuffle y y (shuffle32_from_imm n n n n))) z size @ (VectorSize.Size32x4))
(if-let $true (u64_lt n 4))
(vec_fmla_elem op z x y size n))
(rule 3 (lower_fmla op (bitcast _ (shuffle x x (shuffle64_from_imm n n))) y z size @ (VectorSize.Size64x2))
(if-let $true (u64_lt n 2))
(vec_fmla_elem op z y x size n))
(rule 4 (lower_fmla op x (bitcast _ (shuffle y y (shuffle64_from_imm n n))) z size @ (VectorSize.Size64x2))
(if-let $true (u64_lt n 2))
(vec_fmla_elem op z x y size n))
;; Special case: if one of the multiplicands is `fneg` then peel that away,
;; reverse the operation being performed, and then recurse on `lower_fmla`
;; again to generate the actual instruction.
;;
;; Note that these are the highest priority cases for `lower_fmla` to peel
;; away as many `fneg` operations as possible.
(rule 5 (lower_fmla op (fneg x) y z size)
(lower_fmla (neg_fmla op) x y z size))
(rule 6 (lower_fmla op x (fneg y) z size)
(lower_fmla (neg_fmla op) x y z size))
(decl neg_fmla (VecALUModOp) VecALUModOp)
(rule (neg_fmla (VecALUModOp.Fmla)) (VecALUModOp.Fmls))
(rule (neg_fmla (VecALUModOp.Fmls)) (VecALUModOp.Fmla))
;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (fcopysign x y)))
(fcopy_sign x y ty))
;;;; Rules for `fcvt_to_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint x @ (value_type $F32))))
(fpu_to_int_cvt (FpuToIntOp.F32ToU32) x $false $F32 out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_uint x @ (value_type $F32))))
(fpu_to_int_cvt (FpuToIntOp.F32ToU64) x $false $F32 $I64))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint x @ (value_type $F64))))
(fpu_to_int_cvt (FpuToIntOp.F64ToU32) x $false $F64 out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_uint x @ (value_type $F64))))
(fpu_to_int_cvt (FpuToIntOp.F64ToU64) x $false $F64 $I64))
;;;; Rules for `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint x @ (value_type $F32))))
(fpu_to_int_cvt (FpuToIntOp.F32ToI32) x $true $F32 out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_sint x @ (value_type $F32))))
(fpu_to_int_cvt (FpuToIntOp.F32ToI64) x $true $F32 $I64))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint x @ (value_type $F64))))
(fpu_to_int_cvt (FpuToIntOp.F64ToI32) x $true $F64 out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_sint x @ (value_type $F64))))
(fpu_to_int_cvt (FpuToIntOp.F64ToI64) x $true $F64 $I64))
;;;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_from_uint x @ (value_type (multi_lane 32 _)))))
(vec_misc (VecMisc2.Ucvtf) x (vector_size ty)))
(rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_from_uint x @ (value_type (multi_lane 64 _)))))
(vec_misc (VecMisc2.Ucvtf) x (vector_size ty)))
(rule (lower (has_type $F32 (fcvt_from_uint x @ (value_type (fits_in_32 _)))))
(int_to_fpu (IntToFpuOp.U32ToF32) (put_in_reg_zext32 x)))
(rule (lower (has_type $F64 (fcvt_from_uint x @ (value_type (fits_in_32 _)))))
(int_to_fpu (IntToFpuOp.U32ToF64) (put_in_reg_zext32 x)))
(rule 1 (lower (has_type $F32 (fcvt_from_uint x @ (value_type $I64))))
(int_to_fpu (IntToFpuOp.U64ToF32) x))
(rule 1 (lower (has_type $F64 (fcvt_from_uint x @ (value_type $I64))))
(int_to_fpu (IntToFpuOp.U64ToF64) x))
;;;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_from_sint x @ (value_type (multi_lane 32 _)))))
(vec_misc (VecMisc2.Scvtf) x (vector_size ty)))
(rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_from_sint x @ (value_type (multi_lane 64 _)))))
(vec_misc (VecMisc2.Scvtf) x (vector_size ty)))
(rule (lower (has_type $F32 (fcvt_from_sint x @ (value_type (fits_in_32 _)))))
(int_to_fpu (IntToFpuOp.I32ToF32) (put_in_reg_sext32 x)))
(rule (lower (has_type $F64 (fcvt_from_sint x @ (value_type (fits_in_32 _)))))
(int_to_fpu (IntToFpuOp.I32ToF64) (put_in_reg_sext32 x)))
(rule 1 (lower (has_type $F32 (fcvt_from_sint x @ (value_type $I64))))
(int_to_fpu (IntToFpuOp.I64ToF32) x))
(rule 1 (lower (has_type $F64 (fcvt_from_sint x @ (value_type $I64))))
(int_to_fpu (IntToFpuOp.I64ToF64) x))
;;;; Rules for `fcvt_to_uint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_to_uint_sat x @ (value_type (multi_lane 32 _)))))
(vec_misc (VecMisc2.Fcvtzu) x (vector_size ty)))
(rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_to_uint_sat x @ (value_type (multi_lane 64 _)))))
(vec_misc (VecMisc2.Fcvtzu) x (vector_size ty)))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint_sat x @ (value_type $F32))))
(fpu_to_int_cvt_sat (FpuToIntOp.F32ToU32) x $false out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_uint_sat x @ (value_type $F32))))
(fpu_to_int_cvt_sat (FpuToIntOp.F32ToU64) x $false $I64))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint_sat x @ (value_type $F64))))
(fpu_to_int_cvt_sat (FpuToIntOp.F64ToU32) x $false out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_uint_sat x @ (value_type $F64))))
(fpu_to_int_cvt_sat (FpuToIntOp.F64ToU64) x $false $I64))
;;;; Rules for `fcvt_to_sint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_to_sint_sat x @ (value_type (multi_lane 32 _)))))
(vec_misc (VecMisc2.Fcvtzs) x (vector_size ty)))
(rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_to_sint_sat x @ (value_type (multi_lane 64 _)))))
(vec_misc (VecMisc2.Fcvtzs) x (vector_size ty)))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint_sat x @ (value_type $F32))))
(fpu_to_int_cvt_sat (FpuToIntOp.F32ToI32) x $true out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_sint_sat x @ (value_type $F32))))
(fpu_to_int_cvt_sat (FpuToIntOp.F32ToI64) x $true $I64))
(rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint_sat x @ (value_type $F64))))
(fpu_to_int_cvt_sat (FpuToIntOp.F64ToI32) x $true out_ty))
(rule 1 (lower (has_type $I64 (fcvt_to_sint_sat x @ (value_type $F64))))
(fpu_to_int_cvt_sat (FpuToIntOp.F64ToI64) x $true $I64))
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller
;; Base case, simply subtracting things in registers.
(rule -4 (lower (has_type (fits_in_64 ty) (isub x y)))
(sub ty x y))
;; Special case for when one operand is an immediate that fits in 12 bits.
(rule 0 (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
(sub_imm ty x y))
;; Same as the previous special case, except we can switch the subtraction to an
;; addition if the negated immediate fits in 12 bits.
(rule 2 (lower (has_type (fits_in_64 ty) (isub x y)))
(if-let imm12_neg (imm12_from_negated_value y))
(add_imm ty x imm12_neg))
;; Special cases for when we're subtracting an extended register where the
;; extending operation can get folded into the sub itself.
(rule 1 (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
(sub_extend ty x y))
;; Finally a special case for when we're subtracting the shift of a different
;; register by a constant amount and the shift can get folded into the sub.
(rule -3 (lower (has_type (fits_in_64 ty)
(isub x (ishl y (iconst k)))))
(if-let amt (lshl_from_imm64 ty k))
(sub_shift ty x y amt))
;; vectors
(rule -2 (lower (has_type ty @ (multi_lane _ _) (isub x y)))
(sub_vec x y (vector_size ty)))
;; `i128`
(rule -1 (lower (has_type $I128 (isub x y)))
(sub_i128 x y))
;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_vec128 ty) (uadd_sat x y)))
(uqadd x y (vector_size ty)))
;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_vec128 ty) (sadd_sat x y)))
(sqadd x y (vector_size ty)))
;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_vec128 ty) (usub_sat x y)))
(uqsub x y (vector_size ty)))
;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_vec128 ty) (ssub_sat x y)))
(sqsub x y (vector_size ty)))
;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller.
(rule 1 (lower (has_type (fits_in_64 ty) (ineg x)))
(sub ty (zero_reg) x))
;; `i128`
(rule 2 (lower (has_type $I128 (ineg x)))
(sub_i128 (value_regs_zero) x))
;; vectors.
(rule (lower (has_type (ty_vec128 ty) (ineg x)))
(neg x (vector_size ty)))
;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller.
(rule -3 (lower (has_type (fits_in_64 ty) (imul x y)))
(madd ty x y (zero_reg)))
;; `i128`.
(rule -1 (lower (has_type $I128 (imul x y)))
(let
;; Get the high/low registers for `x`.
((x_regs ValueRegs x)
(x_lo Reg (value_regs_get x_regs 0))
(x_hi Reg (value_regs_get x_regs 1))
;; Get the high/low registers for `y`.
(y_regs ValueRegs y)
(y_lo Reg (value_regs_get y_regs 0))
(y_hi Reg (value_regs_get y_regs 1))
;; 128bit mul formula:
;; dst_lo = x_lo * y_lo
;; dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
;;
;; We can convert the above formula into the following
;; umulh dst_hi, x_lo, y_lo
;; madd dst_hi, x_lo, y_hi, dst_hi
;; madd dst_hi, x_hi, y_lo, dst_hi
;; madd dst_lo, x_lo, y_lo, zero
(dst_hi1 Reg (umulh $I64 x_lo y_lo))
(dst_hi2 Reg (madd $I64 x_lo y_hi dst_hi1))
(dst_hi Reg (madd $I64 x_hi y_lo dst_hi2))
(dst_lo Reg (madd $I64 x_lo y_lo (zero_reg))))
(value_regs dst_lo dst_hi)))
;; Case for i8x16, i16x8, and i32x4.
(rule -2 (lower (has_type (ty_vec128 ty @ (not_i64x2)) (imul x y)))
(mul x y (vector_size ty)))
;; Special lowering for i64x2.
;;
;; This I64X2 multiplication is performed with several 32-bit
;; operations.
;;
;; 64-bit numbers x and y, can be represented as:
;; x = a + 2^32(b)
;; y = c + 2^32(d)
;;
;; A 64-bit multiplication is:
;; x * y = ac + 2^32(ad + bc) + 2^64(bd)
;; note: `2^64(bd)` can be ignored, the value is too large to fit in
;; 64 bits.
;;
;; This sequence implements a I64X2 multiply, where the registers
;; `rn` and `rm` are split up into 32-bit components:
;; rn = |d|c|b|a|
;; rm = |h|g|f|e|
;;
;; rn * rm = |cg + 2^32(ch + dg)|ae + 2^32(af + be)|
;;
;; The sequence is:
;; rev64 rd.4s, rm.4s
;; mul rd.4s, rd.4s, rn.4s
;; xtn tmp1.2s, rn.2d
;; addp rd.4s, rd.4s, rd.4s
;; xtn tmp2.2s, rm.2d
;; shll rd.2d, rd.2s, #32
;; umlal rd.2d, tmp2.2s, tmp1.2s
(rule -1 (lower (has_type $I64X2 (imul x y)))
(let ((rn Reg x)
(rm Reg y)
;; Reverse the 32-bit elements in the 64-bit words.
;; rd = |g|h|e|f|
(rev Reg (rev64 rm (VectorSize.Size32x4)))
;; Calculate the high half components.
;; rd = |dg|ch|be|af|
;;
;; Note that this 32-bit multiply of the high half
;; discards the bits that would overflow, same as
;; if 64-bit operations were used. Also the Shll
;; below would shift out the overflow bits anyway.
(mul Reg (mul rev rn (VectorSize.Size32x4)))
;; Extract the low half components of rn.
;; tmp1 = |c|a|
(tmp1 Reg (xtn rn (ScalarSize.Size32)))
;; Sum the respective high half components.
;; rd = |dg+ch|be+af||dg+ch|be+af|
(sum Reg (addp mul mul (VectorSize.Size32x4)))
;; Extract the low half components of rm.
;; tmp2 = |g|e|
(tmp2 Reg (xtn rm (ScalarSize.Size32)))
;; Shift the high half components, into the high half.
;; rd = |dg+ch << 32|be+af << 32|
(shift Reg (shll32 sum $false))
;; Multiply the low components together, and accumulate with the high
;; half.
;; rd = |rd[1] + cg|rd[0] + ae|
(result Reg (umlal32 shift tmp2 tmp1 $false)))
result))
;; Special case for `i16x8.extmul_low_i8x16_s`.
(rule (lower (has_type $I16X8
(imul (swiden_low x @ (value_type $I8X16))
(swiden_low y @ (value_type $I8X16)))))
(smull8 x y $false))
;; Special case for `i16x8.extmul_high_i8x16_s`.
(rule (lower (has_type $I16X8
(imul (swiden_high x @ (value_type $I8X16))
(swiden_high y @ (value_type $I8X16)))))
(smull8 x y $true))
;; Special case for `i16x8.extmul_low_i8x16_u`.
(rule (lower (has_type $I16X8
(imul (uwiden_low x @ (value_type $I8X16))
(uwiden_low y @ (value_type $I8X16)))))
(umull8 x y $false))
;; Special case for `i16x8.extmul_high_i8x16_u`.
(rule (lower (has_type $I16X8
(imul (uwiden_high x @ (value_type $I8X16))
(uwiden_high y @ (value_type $I8X16)))))
(umull8 x y $true))
;; Special case for `i32x4.extmul_low_i16x8_s`.
(rule (lower (has_type $I32X4
(imul (swiden_low x @ (value_type $I16X8))
(swiden_low y @ (value_type $I16X8)))))
(smull16 x y $false))
;; Special case for `i32x4.extmul_high_i16x8_s`.
(rule (lower (has_type $I32X4
(imul (swiden_high x @ (value_type $I16X8))
(swiden_high y @ (value_type $I16X8)))))
(smull16 x y $true))
;; Special case for `i32x4.extmul_low_i16x8_u`.
(rule (lower (has_type $I32X4
(imul (uwiden_low x @ (value_type $I16X8))
(uwiden_low y @ (value_type $I16X8)))))
(umull16 x y $false))
;; Special case for `i32x4.extmul_high_i16x8_u`.
(rule (lower (has_type $I32X4
(imul (uwiden_high x @ (value_type $I16X8))
(uwiden_high y @ (value_type $I16X8)))))
(umull16 x y $true))
;; Special case for `i64x2.extmul_low_i32x4_s`.
(rule (lower (has_type $I64X2
(imul (swiden_low x @ (value_type $I32X4))
(swiden_low y @ (value_type $I32X4)))))
(smull32 x y $false))
;; Special case for `i64x2.extmul_high_i32x4_s`.
(rule (lower (has_type $I64X2
(imul (swiden_high x @ (value_type $I32X4))
(swiden_high y @ (value_type $I32X4)))))
(smull32 x y $true))
;; Special case for `i64x2.extmul_low_i32x4_u`.
(rule (lower (has_type $I64X2
(imul (uwiden_low x @ (value_type $I32X4))
(uwiden_low y @ (value_type $I32X4)))))
(umull32 x y $false))
;; Special case for `i64x2.extmul_high_i32x4_u`.
(rule (lower (has_type $I64X2
(imul (uwiden_high x @ (value_type $I32X4))
(uwiden_high y @ (value_type $I32X4)))))
(umull32 x y $true))
;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule 1 (lower (has_type $I64 (smulhi x y)))
(smulh $I64 x y))
(rule (lower (has_type (fits_in_32 ty) (smulhi x y)))
(let ((x64 Reg (put_in_reg_sext64 x))
(y64 Reg (put_in_reg_sext64 y))
(mul Reg (madd $I64 x64 y64 (zero_reg)))
(result Reg (asr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
result))
;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule 1 (lower (has_type $I64 (umulhi x y)))
(umulh $I64 x y))
(rule (lower (has_type (fits_in_32 ty) (umulhi x y)))
(let (
(x64 Reg (put_in_reg_zext64 x))
(y64 Reg (put_in_reg_zext64 y))
(mul Reg (madd $I64 x64 y64 (zero_reg)))
(result Reg (lsr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty))))
)
(value_reg result)))
;;;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; TODO: Add UDiv32 to implement 32-bit directly, rather
;; than extending the input.
;;
;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of
;; CLIF's `udiv` the check for zero needs to be manually performed.
(rule (lower (has_type (fits_in_64 ty) (udiv x y)))
(a64_udiv $I64 (put_in_reg_zext64 x) (put_nonzero_in_reg_zext64 y)))
;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
(decl put_nonzero_in_reg_zext64 (Value) Reg)
(rule -1 (put_nonzero_in_reg_zext64 val)
(trap_if_zero_divisor (put_in_reg_zext64 val)))
;; Special case where if a `Value` is known to be nonzero we can trivially
;; move it into a register.
(rule (put_nonzero_in_reg_zext64 (and (value_type ty)
(iconst (nonzero_u64_from_imm64 n))))
(imm ty (ImmExtend.Zero) n))