diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 496e9ee1023b..5a489ee812f0 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -10,12 +10,9 @@
       (rd WritableReg)
       (imm Imm20))
 
-    (LoadConst32
-      (rd WritableReg)
-      (imm u32))
-
-    (LoadConst64
+    (LoadInlineConst
       (rd WritableReg)
+      (ty Type)
       (imm u64))
 
      (Auipc
@@ -1525,6 +1522,7 @@
 ;; Immediate Loading rules
 ;; TODO: Loading the zero reg directly causes a bunch of regalloc errors, we should look into it.
 ;; TODO: We can load constants like 0x3ff0000000000000 by loading the bits then doing a shift left.
+;; TODO: Load floats using `fld` instead of `ld`
 (decl imm (Type u64) Reg)
 
 ;; Refs get loaded as integers.
@@ -1553,10 +1551,12 @@
   (if-let (i64_generate_imm imm20 imm12) (i64_sextend_u64 ty c))
   (rv_addi (rv_lui imm20) imm12))
 
-;; Otherwise we fall back to loading the immediate from memory
-;; TODO: This doesen't yet emit the constant into the memory pool, but it would
-;; be pretty neat if it did.
-(rule 0 (imm (ty_int ty) c) (emit_load_const_64 c))
+;; Otherwise we fall back to loading the immediate from the constant pool.
+(rule 0 (imm (ty_int ty) c)
+  (emit_load
+    (LoadOP.Ld)
+    (mem_flags_trusted)
+    (gen_const_amode (emit_u64_le_const c))))
 
 ;; Imm12 Rules
 
@@ -1679,10 +1679,6 @@
             (_ Unit (emit (MInst.AluRRR op dst src1 src2))))
         dst))
 
-
-(decl pack_float_rounding_mode (FRM) OptionFloatRoundingMode)
-(extern constructor pack_float_rounding_mode pack_float_rounding_mode)
-
 ;; Helper for emitting `MInst.AluRRR` instructions.
 (decl fpu_rrr (FpuOPRRR Type Reg Reg) Reg)
 (rule (fpu_rrr op ty src1 src2)
@@ -1714,12 +1710,6 @@
             (_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
         dst))
 
-;; Helper for emitting the `LoadConst64` instruction.
-(decl emit_load_const_64 (u64) XReg)
-(rule (emit_load_const_64 imm)
-      (let ((dst WritableXReg (temp_writable_xreg))
-            (_ Unit (emit (MInst.LoadConst64 dst imm))))
-        dst))
 
 ;; Helper for emitting the `Lui` instruction.
 ;; TODO: This should be something like `emit_u_type`. And should share the
@@ -2298,24 +2288,28 @@
 (decl gen_const_amode (VCodeConstant) AMode)
 (extern constructor gen_const_amode gen_const_amode)
 
-(decl offset32_imm (i32) Offset32)
-(extern constructor offset32_imm offset32_imm)
+
+;; Returns a canonical type for a LoadOP. We only return I64 or F64.
+(decl load_op_reg_type (LoadOP) Type)
+(rule 1 (load_op_reg_type (LoadOP.Fld)) $F64)
+(rule 1 (load_op_reg_type (LoadOP.Flw)) $F64)
+(rule 0 (load_op_reg_type _) $I64)
+
+(decl emit_load (LoadOP MemFlags AMode) Reg)
+(rule (emit_load op flags from)
+      (let ((dst WritableReg (temp_writable_reg (load_op_reg_type op)))
+            (_ Unit (emit (MInst.Load dst op flags from))))
+        dst))
 
 ;; helper function to load from memory.
 (decl gen_load (Reg Offset32 LoadOP MemFlags Type) Reg)
-(rule
-  (gen_load p offset op flags ty)
-  (let
-    ((tmp WritableReg (temp_writable_reg ty))
-      (_ Unit (emit (MInst.Load tmp op flags (gen_amode p offset $I64)))))
-    tmp))
+(rule (gen_load p offset op flags ty)
+  (emit_load op flags (gen_amode p offset $I64)))
 
 (decl gen_load_128 (Reg Offset32 MemFlags) ValueRegs)
-(rule
-  (gen_load_128 p offset flags)
-  (let
-    ((low Reg (gen_load p offset (LoadOP.Ld) flags $I64))
-      (high Reg (gen_load p (offset32_add offset 8) (LoadOP.Ld) flags $I64)))
+(rule (gen_load_128 p offset flags)
+  (let ((low Reg (gen_load p offset (LoadOP.Ld) flags $I64))
+        (high Reg (gen_load p (offset32_add offset 8) (LoadOP.Ld) flags $I64)))
     (value_regs low high)))
 
 (decl default_memflags () MemFlags)
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index 82f7ee79dadb..f86569b24323 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -25,78 +25,6 @@ impl EmitInfo {
     }
 }
 
-/// load constant by put the constant in the code stream.
-/// calculate the pc and using load instruction.
-/// This is only allow used in the emit stage.
-/// Because of those instruction must execute together.
-/// see https://github.com/bytecodealliance/wasmtime/pull/5612
-#[derive(Clone, Copy)]
-pub(crate) enum LoadConstant {
-    U32(u32),
-    U64(u64),
-}
-
-impl LoadConstant {
-    fn to_le_bytes(self) -> Vec<u8> {
-        match self {
-            LoadConstant::U32(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
-            LoadConstant::U64(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
-        }
-    }
-    fn load_op(self) -> LoadOP {
-        match self {
-            LoadConstant::U32(_) => LoadOP::Lwu,
-            LoadConstant::U64(_) => LoadOP::Ld,
-        }
-    }
-    fn load_ty(self) -> Type {
-        match self {
-            LoadConstant::U32(_) => R32,
-            LoadConstant::U64(_) => R64,
-        }
-    }
-
-    pub(crate) fn load_constant<F: FnMut(Type) -> Writable<Reg>>(
-        self,
-        rd: Writable<Reg>,
-        alloc_tmp: &mut F,
-    ) -> SmallInstVec<Inst> {
-        let mut insts = SmallInstVec::new();
-        // get current pc.
-        let pc = alloc_tmp(I64);
-        insts.push(Inst::Auipc {
-            rd: pc,
-            imm: Imm20 { bits: 0 },
-        });
-        // load
-        insts.push(Inst::Load {
-            rd,
-            op: self.load_op(),
-            flags: MemFlags::new(),
-            from: AMode::RegOffset(pc.to_reg(), 12, self.load_ty()),
-        });
-        let data = self.to_le_bytes();
-        // jump over.
-        insts.push(Inst::Jal {
-            dest: BranchTarget::ResolvedOffset(Inst::INSTRUCTION_SIZE + data.len() as i32),
-        });
-        insts.push(Inst::RawData { data });
-        insts
-    }
-
-    // load and perform an extra add.
-    pub(crate) fn load_constant_and_add(self, rd: Writable<Reg>, rs: Reg) -> SmallInstVec<Inst> {
-        let mut insts = self.load_constant(rd, &mut |_| rd);
-        insts.push(Inst::AluRRR {
-            alu_op: AluOPRRR::Add,
-            rd,
-            rs1: rd.to_reg(),
-            rs2: rs,
-        });
-        insts
-    }
-}
-
 pub(crate) fn reg_to_gpr_num(m: Reg) -> u32 {
     u32::try_from(m.to_real_reg().unwrap().hw_enc() & 31).unwrap()
 }
@@ -399,8 +327,7 @@ impl Inst {
             | Inst::BrTable { .. }
             | Inst::Auipc { .. }
             | Inst::Lui { .. }
-            | Inst::LoadConst32 { .. }
-            | Inst::LoadConst64 { .. }
+            | Inst::LoadInlineConst { .. }
             | Inst::AluRRR { .. }
             | Inst::FpuRRR { .. }
             | Inst::AluRRImm12 { .. }
@@ -533,19 +460,34 @@ impl MachInstEmit for Inst {
                 let x: u32 = 0b0110111 | reg_to_gpr_num(rd.to_reg()) << 7 | (imm.as_u32() << 12);
                 sink.put4(x);
             }
-            &Inst::LoadConst32 { rd, imm } => {
+            &Inst::LoadInlineConst { rd, ty, imm } => {
                 let rd = allocs.next_writable(rd);
-                LoadConstant::U32(imm)
-                    .load_constant(rd, &mut |_| rd)
-                    .into_iter()
-                    .for_each(|inst| inst.emit(&[], sink, emit_info, state));
-            }
-            &Inst::LoadConst64 { rd, imm } => {
-                let rd = allocs.next_writable(rd);
-                LoadConstant::U64(imm)
-                    .load_constant(rd, &mut |_| rd)
-                    .into_iter()
-                    .for_each(|inst| inst.emit(&[], sink, emit_info, state));
+
+                let data = &imm.to_le_bytes()[..ty.bytes() as usize];
+
+                let label_data: MachLabel = sink.get_label();
+                let label_end: MachLabel = sink.get_label();
+
+                // Load into rd
+                Inst::Load {
+                    rd,
+                    op: LoadOP::from_type(ty),
+                    flags: MemFlags::new(),
+                    from: AMode::Label(label_data),
+                }
+                .emit(&[], sink, emit_info, state);
+
+                // Jump over the inline pool
+                Inst::Jal {
+                    dest: BranchTarget::Label(label_end),
+                }
+                .emit(&[], sink, emit_info, state);
+
+                // Emit the inline data
+                sink.bind_label(label_data, &mut state.ctrl_plane);
+                Inst::RawData { data: data.into() }.emit(&[], sink, emit_info, state);
+
+                sink.bind_label(label_end, &mut state.ctrl_plane);
             }
             &Inst::FpuRR {
                 frm,
@@ -666,6 +608,8 @@ impl MachInstEmit for Inst {
                 let offset = from.get_offset_with_state(state);
                 let offset_imm12 = Imm12::maybe_from_i64(offset);
 
+                // TODO: We shouldn't just fall back to `LoadAddr` immediately. For `MachLabel`s
+                // we should try to emit the `auipc` and add a relocation on this load.
                 let (addr, imm12) = match (base, offset_imm12) {
                     // If the offset fits into an imm12 we can directly encode it.
                     (Some(base), Some(imm12)) => (base, imm12),
@@ -693,6 +637,8 @@ impl MachInstEmit for Inst {
                 let offset = to.get_offset_with_state(state);
                 let offset_imm12 = Imm12::maybe_from_i64(offset);
 
+                // TODO: We shouldn't just fall back to `LoadAddr` immediately. For `MachLabel`s
+                // we should try to emit the `auipc` and add a relocation on this store.
                 let (addr, imm12) = match (base, offset_imm12) {
                     // If the offset fits into an imm12 we can directly encode it.
                     (Some(base), Some(imm12)) => (base, imm12),
@@ -1265,8 +1211,14 @@ impl MachInstEmit for Inst {
                         .emit(&[], sink, emit_info, state);
                     }
                     (_, Some(rs), None) => {
-                        LoadConstant::U64(offset as u64)
-                            .load_constant_and_add(rd, rs)
+                        let mut insts = Inst::load_constant_u64(rd, offset as u64);
+                        insts.push(Inst::AluRRR {
+                            alu_op: AluOPRRR::Add,
+                            rd,
+                            rs1: rd.to_reg(),
+                            rs2: rs,
+                        });
+                        insts
                             .into_iter()
                             .for_each(|inst| inst.emit(&[], sink, emit_info, state));
                     }
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index d63227854f1f..6a136d9b6a74 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -227,16 +227,23 @@ impl Inst {
     pub(crate) fn load_constant_u32(rd: Writable<Reg>, value: u64) -> SmallInstVec<Inst> {
         let insts = Inst::load_const_imm(rd, value);
         insts.unwrap_or_else(|| {
-            smallvec![Inst::LoadConst32 {
+            smallvec![Inst::LoadInlineConst {
                 rd,
-                imm: value as u32
+                ty: I32,
+                imm: value
             }]
         })
     }
 
     pub fn load_constant_u64(rd: Writable<Reg>, value: u64) -> SmallInstVec<Inst> {
         let insts = Inst::load_const_imm(rd, value);
-        insts.unwrap_or_else(|| smallvec![Inst::LoadConst64 { rd, imm: value }])
+        insts.unwrap_or_else(|| {
+            smallvec![Inst::LoadInlineConst {
+                rd,
+                ty: I64,
+                imm: value
+            }]
+        })
     }
 
     pub(crate) fn construct_auipc_and_jalr(
@@ -377,8 +384,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
         }
         &Inst::Auipc { rd, .. } => collector.reg_def(rd),
         &Inst::Lui { rd, .. } => collector.reg_def(rd),
-        &Inst::LoadConst32 { rd, .. } => collector.reg_def(rd),
-        &Inst::LoadConst64 { rd, .. } => collector.reg_def(rd),
+        &Inst::LoadInlineConst { rd, .. } => collector.reg_def(rd),
         &Inst::AluRRR { rd, rs1, rs2, .. } => {
             collector.reg_use(rs1);
             collector.reg_use(rs2);
@@ -958,7 +964,7 @@ impl MachInst for Inst {
 
     fn worst_case_size() -> CodeOffset {
         // calculate by test function riscv64_worst_case_instruction_size()
-        116
+        124
     }
 
     fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {
@@ -1371,16 +1377,7 @@ impl Inst {
             &Inst::Lui { rd, ref imm } => {
                 format!("{} {},{}", "lui", format_reg(rd.to_reg(), allocs), imm.bits)
             }
-            &Inst::LoadConst32 { rd, imm } => {
-                let rd = format_reg(rd.to_reg(), allocs);
-                let mut buf = String::new();
-                write!(&mut buf, "auipc {},0; ", rd).unwrap();
-                write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
-                write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 4).unwrap();
-                write!(&mut buf, ".4byte 0x{:x}", imm).unwrap();
-                buf
-            }
-            &Inst::LoadConst64 { rd, imm } => {
+            &Inst::LoadInlineConst { rd, imm, .. } => {
                 let rd = format_reg(rd.to_reg(), allocs);
                 let mut buf = String::new();
                 write!(&mut buf, "auipc {},0; ", rd).unwrap();
diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
index eb3090400337..4ce9a4c49836 100644
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@@ -440,17 +440,10 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
         self.backend.isa_flags.has_zbs()
     }
 
-    fn offset32_imm(&mut self, offset: i32) -> Offset32 {
-        Offset32::new(offset)
-    }
     fn default_memflags(&mut self) -> MemFlags {
         MemFlags::new()
     }
 
-    fn pack_float_rounding_mode(&mut self, f: &FRM) -> OptionFloatRoundingMode {
-        Some(*f)
-    }
-
     fn int_convert_2_float_op(&mut self, from: Type, is_signed: bool, to: Type) -> FpuOPRR {
         FpuOPRR::int_convert_2_float_op(from, is_signed, to)
     }
diff --git a/cranelift/filetests/filetests/isa/riscv64/constants.clif b/cranelift/filetests/filetests/isa/riscv64/constants.clif
index 174aef40d6cb..9a1afa3b29df 100644
--- a/cranelift/filetests/filetests/isa/riscv64/constants.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif
@@ -76,17 +76,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0x00, 0x00, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -96,17 +96,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff00000000
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0x00, 0x00
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -116,17 +116,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff000000000000
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xff, 0xff
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -168,17 +168,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffff0000ffff
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0xff, 0xff, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0xff, 0xff
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -188,17 +188,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000ffffffff
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0xff, 0xff, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0xff, 0xff
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -208,17 +208,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffffffff
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0xff, 0xff, 0xff, 0xff
 ;   .byte 0xff, 0xff, 0x00, 0x00
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -228,17 +228,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xf34bf0a31212003a
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0x3a, 0x00, 0x12, 0x12
 ;   .byte 0xa3, 0xf0, 0x4b, 0xf3
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -248,17 +248,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e900001ef40000
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0x00, 0x00, 0xf4, 0x1e
 ;   .byte 0x00, 0x00, 0xe9, 0x12
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -268,17 +268,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e9ffff1ef4ffff
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0xff, 0xff, 0xf4, 0x1e
 ;   .byte 0xff, 0xff, 0xe9, 0x12
-;   ret
 
 function %f() -> i32 {
 block0:
@@ -320,17 +320,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xfffffff7
+;   ld a0,[const(0)]
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
+;   auipc t6, 0
+;   addi t6, t6, 0x10
+;   ld a0, 0(t6)
+;   ret
 ;   .byte 0xf7, 0xff, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ret
 
 function %f() -> i64 {
 block0:
@@ -356,19 +356,20 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0x3ff0000000000000
+;   ld t0,[const(0)]
 ;   fmv.d.x fa0,t0
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0xf0, 0x3f
+;   auipc t6, 0
+;   addi t6, t6, 0x18
+;   ld t0, 0(t6)
 ;   fmv.d.x fa0, t0
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0x3f
 
 function %f() -> f32 {
 block0:
@@ -396,19 +397,20 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0x4049000000000000
+;   ld t0,[const(0)]
 ;   fmv.d.x fa0,t0
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x49, 0x40
+;   auipc t6, 0
+;   addi t6, t6, 0x18
+;   ld t0, 0(t6)
 ;   fmv.d.x fa0, t0
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x49, 0x40
 
 function %f() -> f32 {
 block0:
@@ -472,19 +474,20 @@ block0:
 
 ; VCode:
 ; block0:
-;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xc030000000000000
+;   ld t0,[const(0)]
 ;   fmv.d.x fa0,t0
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x30, 0xc0
+;   auipc t6, 0
+;   addi t6, t6, 0x18
+;   ld t0, 0(t6)
 ;   fmv.d.x fa0, t0
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x30, 0xc0
 
 function %f() -> f32 {
 block0:
diff --git a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
index 34753117266f..feb8e7c7d452 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
@@ -92,9 +92,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -125,9 +126,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -136,7 +138,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x70, 0x40
@@ -163,9 +166,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -196,9 +200,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -207,7 +212,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x40
diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif
index dedccb1dd783..bf33bab5cf5d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/float.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/float.clif
@@ -453,9 +453,10 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x38
+;   beqz a0, 0x3c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -519,9 +520,10 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x38
+;   beqz a0, 0x3c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -585,9 +587,10 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x38
+;   beqz a0, 0x3c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -651,9 +654,10 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x38
+;   beqz a0, 0x3c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -748,9 +752,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -781,9 +786,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x01, 0x00, 0x00, 0xcf
 ;   fmv.w.x ft3, t6
@@ -814,9 +820,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -847,9 +854,10 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x40
+;   beqz a0, 0x44
 ;   auipc t6, 0
-;   lwu t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   lw t6, 0(t6)
 ;   j 8
 ;   .byte 0x01, 0x00, 0x00, 0xdf
 ;   fmv.w.x ft3, t6
@@ -880,9 +888,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -891,7 +900,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x41
@@ -918,9 +928,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x20, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0xc1
@@ -929,7 +940,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0x41
@@ -956,9 +968,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -967,7 +980,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x43
@@ -994,9 +1008,10 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x54
+;   beqz a0, 0x5c
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x01, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0xc3
@@ -1005,7 +1020,8 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   ld t6, 0xc(t6)
+;   addi t6, t6, 0x10
+;   ld t6, 0(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0x43
diff --git a/cranelift/filetests/filetests/isa/riscv64/return-call.clif b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
index 2691e2fd6ed5..f09e9bf611e7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
@@ -96,21 +96,21 @@ block0(v0: f64):
 
 ; VCode:
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x4030000000000000
+;   ld a0,[const(0)]
 ;   fmv.d.x ft5,a0
 ;   fadd.d ft0,ft0,ft5
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc a0, 0
-;   ld a0, 0xc(a0)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x30, 0x40
+;   auipc t6, 0
+;   addi t6, t6, 0x18
+;   ld a0, 0(t6)
 ;   fmv.d.x ft5, a0
 ;   fadd.d ft0, ft0, ft5
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x30, 0x40
 
 function %call_f64(f64) -> f64 tail {
     fn0 = %callee_f64(f64) -> f64 tail
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif b/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
index eef98e78f2f3..d3805bfb9a6e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
@@ -19,7 +19,7 @@ block0(v0: f64x2, v1: f64x2):
 ;   vmfeq.vv v6,v1,v1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmfeq.vv v8,v3,v3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmand.mm v0,v6,v8 #avl=2, #vtype=(e64, m1, ta, ma)
-;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0x7ff8000000000000
+;   ld t4,[const(0)]
 ;   vmv.v.x v14,t4 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vfmax.vv v16,v1,v3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmerge.vvm v18,v14,v16,v0.t #avl=2, #vtype=(e64, m1, ta, ma)
@@ -45,11 +45,9 @@ block0(v0: f64x2, v1: f64x2):
 ;   .byte 0x57, 0x93, 0x10, 0x62
 ;   .byte 0x57, 0x94, 0x31, 0x62
 ;   .byte 0x57, 0x20, 0x64, 0x66
-;   auipc t4, 0
-;   ld t4, 0xc(t4)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0xf8, 0x7f
+;   auipc t6, 0
+;   addi t6, t6, 0x34
+;   ld t4, 0(t6)
 ;   .byte 0x57, 0xc7, 0x0e, 0x5e
 ;   .byte 0x57, 0x98, 0x11, 0x1a
 ;   .byte 0x57, 0x09, 0xe8, 0x5c
@@ -59,6 +57,9 @@ block0(v0: f64x2, v1: f64x2):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf8, 0x7f
 
 function %fmax_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif b/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
index 6a8d643db748..80fe5210dc69 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
@@ -19,7 +19,7 @@ block0(v0: f64x2, v1: f64x2):
 ;   vmfeq.vv v6,v1,v1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmfeq.vv v8,v3,v3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmand.mm v0,v6,v8 #avl=2, #vtype=(e64, m1, ta, ma)
-;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0x7ff8000000000000
+;   ld t4,[const(0)]
 ;   vmv.v.x v14,t4 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vfmin.vv v16,v1,v3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vmerge.vvm v18,v14,v16,v0.t #avl=2, #vtype=(e64, m1, ta, ma)
@@ -45,11 +45,9 @@ block0(v0: f64x2, v1: f64x2):
 ;   .byte 0x57, 0x93, 0x10, 0x62
 ;   .byte 0x57, 0x94, 0x31, 0x62
 ;   .byte 0x57, 0x20, 0x64, 0x66
-;   auipc t4, 0
-;   ld t4, 0xc(t4)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0xf8, 0x7f
+;   auipc t6, 0
+;   addi t6, t6, 0x34
+;   ld t4, 0(t6)
 ;   .byte 0x57, 0xc7, 0x0e, 0x5e
 ;   .byte 0x57, 0x98, 0x11, 0x12
 ;   .byte 0x57, 0x09, 0xe8, 0x5c
@@ -59,6 +57,9 @@ block0(v0: f64x2, v1: f64x2):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf8, 0x7f
 
 function %fmin_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif b/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
index edbb4edbc2f6..02ea0cb5766d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
@@ -16,12 +16,12 @@ block0(v0: i8x16, v1: i8x16):
 ; block0:
 ;   vle8.v v1,16(fp) #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vle8.v v3,32(fp) #avl=16, #vtype=(e8, m1, ta, ma)
-;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0x5555555555555555
+;   ld a3,[const(0)]
 ;   vmv.s.x v8,a3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v12,v1,v8 #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vcompress.vm v13,v3,v8 #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vslideup.vi v12,v13,8 #avl=16, #vtype=(e8, m1, ta, ma)
-;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xaaaaaaaaaaaaaaaa
+;   ld a1,[const(1)]
 ;   vmv.s.x v18,a1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v22,v1,v18 #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vcompress.vm v23,v3,v18 #avl=16, #vtype=(e8, m1, ta, ma)
@@ -45,22 +45,18 @@ block0(v0: i8x16, v1: i8x16):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc a3, 0
-;   ld a3, 0xc(a3)
-;   j 0xc
-;   .byte 0x55, 0x55, 0x55, 0x55
-;   .byte 0x55, 0x55, 0x55, 0x55
+;   auipc t6, 0
+;   addi t6, t6, 0x64
+;   ld a3, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x08, 0xcc
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd4, 0x3a
-;   auipc a1, 0
-;   ld a1, 0xc(a1)
-;   j 0xc
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   auipc t6, 0
+;   addi t6, t6, 0x48
+;   ld a1, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x08, 0xcc
@@ -73,6 +69,11 @@ block0(v0: i8x16, v1: i8x16):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
 
 function %iadd_pairwise_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -88,12 +89,12 @@ block0(v0: i16x8, v1: i16x8):
 ; block0:
 ;   vle8.v v1,16(fp) #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vle8.v v3,32(fp) #avl=16, #vtype=(e8, m1, ta, ma)
-;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0x5555555555555555
+;   ld a3,[const(0)]
 ;   vmv.s.x v8,a3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v12,v1,v8 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vcompress.vm v13,v3,v8 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vslideup.vi v12,v13,4 #avl=8, #vtype=(e16, m1, ta, ma)
-;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xaaaaaaaaaaaaaaaa
+;   ld a1,[const(1)]
 ;   vmv.s.x v18,a1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v22,v1,v18 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vcompress.vm v23,v3,v18 #avl=8, #vtype=(e16, m1, ta, ma)
@@ -117,22 +118,18 @@ block0(v0: i16x8, v1: i16x8):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc a3, 0
-;   ld a3, 0xc(a3)
-;   j 0xc
-;   .byte 0x55, 0x55, 0x55, 0x55
-;   .byte 0x55, 0x55, 0x55, 0x55
+;   auipc t6, 0
+;   addi t6, t6, 0x64
+;   ld a3, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x84, 0xcc
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd2, 0x3a
-;   auipc a1, 0
-;   ld a1, 0xc(a1)
-;   j 0xc
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   auipc t6, 0
+;   addi t6, t6, 0x48
+;   ld a1, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x84, 0xcc
@@ -146,6 +143,10 @@ block0(v0: i16x8, v1: i16x8):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
 
 function %iadd_pairwise_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -161,12 +162,12 @@ block0(v0: i32x4, v1: i32x4):
 ; block0:
 ;   vle8.v v1,16(fp) #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vle8.v v3,32(fp) #avl=16, #vtype=(e8, m1, ta, ma)
-;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0x5555555555555555
+;   ld a3,[const(0)]
 ;   vmv.s.x v8,a3 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v12,v1,v8 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vcompress.vm v13,v3,v8 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vslideup.vi v12,v13,2 #avl=4, #vtype=(e32, m1, ta, ma)
-;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xaaaaaaaaaaaaaaaa
+;   ld a1,[const(1)]
 ;   vmv.s.x v18,a1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vcompress.vm v22,v1,v18 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vcompress.vm v23,v3,v18 #avl=4, #vtype=(e32, m1, ta, ma)
@@ -190,22 +191,18 @@ block0(v0: i32x4, v1: i32x4):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc a3, 0
-;   ld a3, 0xc(a3)
-;   j 0xc
-;   .byte 0x55, 0x55, 0x55, 0x55
-;   .byte 0x55, 0x55, 0x55, 0x55
+;   auipc t6, 0
+;   addi t6, t6, 0x64
+;   ld a3, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x02, 0xcd
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd1, 0x3a
-;   auipc a1, 0
-;   ld a1, 0xc(a1)
-;   j 0xc
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
-;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   auipc t6, 0
+;   addi t6, t6, 0x48
+;   ld a1, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x02, 0xcd
@@ -219,4 +216,8 @@ block0(v0: i32x4, v1: i32x4):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
+;   .byte 0xaa, 0xaa, 0xaa, 0xaa
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif b/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
index 67ee555548f5..40246e80ea1f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
@@ -240,20 +240,20 @@ block0(v0: i64x2):
 ;   mv fp,sp
 ; block0:
 ;   vle8.v v1,16(fp) #avl=16, #vtype=(e8, m1, ta, ma)
-;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0x5555555555555555
+;   ld a1,[const(0)]
 ;   vsrl.vi v6,v1,1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vand.vx v8,v6,a1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vsub.vv v10,v1,v8 #avl=2, #vtype=(e64, m1, ta, ma)
-;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0x3333333333333333
+;   ld t4,[const(1)]
 ;   vsrl.vi v14,v10,2 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vand.vx v16,v14,t4 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vand.vx v18,v10,t4 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vadd.vv v20,v18,v16 #avl=2, #vtype=(e64, m1, ta, ma)
-;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xf0f0f0f0f0f0f0f
+;   ld a6,[const(2)]
 ;   vsrl.vi v24,v20,4 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vadd.vv v26,v20,v24 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   vand.vx v28,v26,a6 #avl=2, #vtype=(e64, m1, ta, ma)
-;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0x101010101010101
+;   ld a1,[const(3)]
 ;   vmul.vx v0,v28,a1 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   li a5,56
 ;   vsrl.vx v4,v0,a5 #avl=2, #vtype=(e64, m1, ta, ma)
@@ -273,37 +273,29 @@ block0(v0: i64x2):
 ;   .byte 0x57, 0x70, 0x08, 0xcc
 ;   addi t6, s0, 0x10
 ;   .byte 0x87, 0x80, 0x0f, 0x02
-;   auipc a1, 0
-;   ld a1, 0xc(a1)
-;   j 0xc
-;   .byte 0x55, 0x55, 0x55, 0x55
-;   .byte 0x55, 0x55, 0x55, 0x55
+;   auipc t6, 0
+;   addi t6, t6, 0x84
+;   ld a1, 0(t6)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xb3, 0x10, 0xa2
 ;   .byte 0x57, 0xc4, 0x65, 0x26
 ;   .byte 0x57, 0x05, 0x14, 0x0a
-;   auipc t4, 0
-;   ld t4, 0xc(t4)
-;   j 0xc
-;   .byte 0x33, 0x33, 0x33, 0x33
-;   .byte 0x33, 0x33, 0x33, 0x33
+;   auipc t6, 0
+;   addi t6, t6, 0x70
+;   ld t4, 0(t6)
 ;   .byte 0x57, 0x37, 0xa1, 0xa2
 ;   .byte 0x57, 0xc8, 0xee, 0x26
 ;   .byte 0x57, 0xc9, 0xae, 0x26
 ;   .byte 0x57, 0x0a, 0x28, 0x03
-;   auipc a6, 0
-;   ld a6, 0xc(a6)
-;   j 0xc
-;   .byte 0x0f, 0x0f, 0x0f, 0x0f
-;   .byte 0x0f, 0x0f, 0x0f, 0x0f
+;   auipc t6, 0
+;   addi t6, t6, 0x5c
+;   ld a6, 0(t6)
 ;   .byte 0x57, 0x3c, 0x42, 0xa3
 ;   .byte 0x57, 0x0d, 0x4c, 0x03
 ;   .byte 0x57, 0x4e, 0xa8, 0x27
-;   auipc a1, 0
-;   ld a1, 0xc(a1)
-;   j 0xc
-;   .byte 0x01, 0x01, 0x01, 0x01
-;   .byte 0x01, 0x01, 0x01, 0x01
+;   auipc t6, 0
+;   addi t6, t6, 0x4c
+;   ld a1, 0(t6)
 ;   .byte 0x57, 0xe0, 0xc5, 0x97
 ;   addi a5, zero, 0x38
 ;   .byte 0x57, 0xc2, 0x07, 0xa2
@@ -313,4 +305,13 @@ block0(v0: i64x2):
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0x55, 0x55, 0x55, 0x55
+;   .byte 0x33, 0x33, 0x33, 0x33
+;   .byte 0x33, 0x33, 0x33, 0x33
+;   .byte 0x0f, 0x0f, 0x0f, 0x0f
+;   .byte 0x0f, 0x0f, 0x0f, 0x0f
+;   .byte 0x01, 0x01, 0x01, 0x01
+;   .byte 0x01, 0x01, 0x01, 0x01
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
index 0364fcb82bf8..3467fcf31dfa 100644
--- a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
@@ -379,18 +379,15 @@ block0(v0: i64):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
-;   auipc t6, 0
-;   ld t6, 0xc(t6)
-;   j 0xc
-;   .byte 0x80, 0x1a, 0x06, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
+;   lui t6, 0x62
+;   addi t6, t6, -0x580
 ;   add t6, t6, a0
 ;   ld t6, 0(t6)
 ;   addi t6, t6, 0x20
 ;   bgeu sp, t6, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
 ;   addi sp, sp, -0x20
-; block1: ; offset 0x3c
+; block1: ; offset 0x30
 ;   addi sp, sp, 0x20
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 820e72762fd6..66de83f9c3af 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   slli t0,a0,32
 ;;   srli t2,t0,32
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   ld t1,[const(1)]
 ;;   add t0,t2,t1
 ;;   ult a0,t0,t2##ty=i64
 ;;   trap_if a0,heap_oob
@@ -53,7 +53,7 @@
 ;; block1:
 ;;   ld a0,0(a2)
 ;;   add a0,a0,t2
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   ld a2,[const(0)]
 ;;   add a0,a0,a2
 ;;   sw a1,0(a0)
 ;;   j label2
@@ -66,7 +66,7 @@
 ;; block0:
 ;;   slli t0,a0,32
 ;;   srli t2,t0,32
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   ld t1,[const(1)]
 ;;   add t0,t2,t1
 ;;   ult a0,t0,t2##ty=i64
 ;;   trap_if a0,heap_oob
@@ -76,7 +76,7 @@
 ;; block1:
 ;;   ld a0,0(a1)
 ;;   add a0,a0,t2
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   ld a1,[const(0)]
 ;;   add a0,a0,a1
 ;;   lw a0,0(a0)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 3318a9b1d6a1..d4ebf3e8ac11 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   slli t0,a0,32
 ;;   srli t2,t0,32
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   ld t1,[const(1)]
 ;;   add t0,t2,t1
 ;;   ult a0,t0,t2##ty=i64
 ;;   trap_if a0,heap_oob
@@ -53,7 +53,7 @@
 ;; block1:
 ;;   ld a0,0(a2)
 ;;   add a0,a0,t2
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   ld a2,[const(0)]
 ;;   add a0,a0,a2
 ;;   sb a1,0(a0)
 ;;   j label2
@@ -66,7 +66,7 @@
 ;; block0:
 ;;   slli t0,a0,32
 ;;   srli t2,t0,32
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   ld t1,[const(1)]
 ;;   add t0,t2,t1
 ;;   ult a0,t0,t2##ty=i64
 ;;   trap_if a0,heap_oob
@@ -76,7 +76,7 @@
 ;; block1:
 ;;   ld a0,0(a1)
 ;;   add a0,a0,t2
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   ld a1,[const(0)]
 ;;   add a0,a0,a1
 ;;   lbu a0,0(a0)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index bb494a2e0f56..e501ff65a092 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
-;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
+;;   ld a6,[const(1)]
 ;;   add a5,a7,a6
 ;;   ult t3,a5,a7##ty=i64
 ;;   trap_if t3,heap_oob
@@ -51,7 +51,7 @@
 ;;   ugt t3,a5,t3##ty=i64
 ;;   ld t4,0(a2)
 ;;   add a7,t4,a7
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   ld t4,[const(0)]
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a2,t3,255
@@ -70,7 +70,7 @@
 ;; block0:
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
-;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
+;;   ld a6,[const(1)]
 ;;   add a5,a7,a6
 ;;   ult t3,a5,a7##ty=i64
 ;;   trap_if t3,heap_oob
@@ -78,7 +78,7 @@
 ;;   ugt t3,a5,t3##ty=i64
 ;;   ld t4,0(a1)
 ;;   add a7,t4,a7
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   ld t4,[const(0)]
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a1,t3,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 5aa80eeb8d2b..40f11e0804c8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
-;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
+;;   ld a6,[const(1)]
 ;;   add a5,a7,a6
 ;;   ult t3,a5,a7##ty=i64
 ;;   trap_if t3,heap_oob
@@ -51,7 +51,7 @@
 ;;   ugt t3,a5,t3##ty=i64
 ;;   ld t4,0(a2)
 ;;   add a7,t4,a7
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   ld t4,[const(0)]
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a2,t3,255
@@ -70,7 +70,7 @@
 ;; block0:
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
-;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
+;;   ld a6,[const(1)]
 ;;   add a5,a7,a6
 ;;   ult t3,a5,a7##ty=i64
 ;;   trap_if t3,heap_oob
@@ -78,7 +78,7 @@
 ;;   ugt t3,a5,t3##ty=i64
 ;;   ld t4,0(a1)
 ;;   add a7,t4,a7
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   ld t4,[const(0)]
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a1,t3,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 39dda859af1e..3fd3abd0038e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -49,7 +49,7 @@
 ;; block1:
 ;;   ld t0,0(a2)
 ;;   add t4,t0,t4
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   ld t0,[const(0)]
 ;;   add t4,t4,t0
 ;;   sw a1,0(t4)
 ;;   j label2
@@ -68,7 +68,7 @@
 ;; block1:
 ;;   ld t0,0(a1)
 ;;   add t4,t0,t4
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   ld t0,[const(0)]
 ;;   add t4,t4,t0
 ;;   lw a0,0(t4)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6caf11f388fd..d4e7ea4ac5f2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -49,7 +49,7 @@
 ;; block1:
 ;;   ld t0,0(a2)
 ;;   add t4,t0,t4
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   ld t0,[const(0)]
 ;;   add t4,t4,t0
 ;;   sb a1,0(t4)
 ;;   j label2
@@ -68,7 +68,7 @@
 ;; block1:
 ;;   ld t0,0(a1)
 ;;   add t4,t0,t4
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   ld t0,[const(0)]
 ;;   add t4,t4,t0
 ;;   lbu a0,0(t4)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 08fbad1904ca..6bad86637423 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;;   ugt a4,a5,a3##ty=i64
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
-;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   ld a5,[const(0)]
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
@@ -70,7 +70,7 @@
 ;;   ugt a4,a5,a3##ty=i64
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
-;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   ld a5,[const(0)]
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c5fac9a92678..97b1c288783f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;;   ugt a4,a5,a3##ty=i64
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
-;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   ld a5,[const(0)]
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
@@ -70,7 +70,7 @@
 ;;   ugt a4,a5,a3##ty=i64
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
-;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   ld a5,[const(0)]
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index e4ad3ee89014..49a6f841d864 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   ld t4,[const(1)]
 ;;   add t3,a0,t4
 ;;   ult t0,t3,a0##ty=i64
 ;;   trap_if t0,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
+;;   ld t2,[const(0)]
 ;;   add t1,t1,t2
 ;;   sw a1,0(t1)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   ld t4,[const(1)]
 ;;   add t3,a0,t4
 ;;   ult t0,t3,a0##ty=i64
 ;;   trap_if t0,heap_oob
@@ -72,7 +72,7 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
+;;   ld t2,[const(0)]
 ;;   add t1,t1,t2
 ;;   lw a0,0(t1)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6bb92fd9cb46..2fa74c054dbd 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   ld t4,[const(1)]
 ;;   add t3,a0,t4
 ;;   ult t0,t3,a0##ty=i64
 ;;   trap_if t0,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
+;;   ld t2,[const(0)]
 ;;   add t1,t1,t2
 ;;   sb a1,0(t1)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   ld t4,[const(1)]
 ;;   add t3,a0,t4
 ;;   ult t0,t3,a0##ty=i64
 ;;   trap_if t0,heap_oob
@@ -72,7 +72,7 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
+;;   ld t2,[const(0)]
 ;;   add t1,t1,t2
 ;;   lbu a0,0(t1)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 711ee993b425..f6bcce9ade01 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
+;;   ld a4,[const(1)]
 ;;   add a3,a0,a4
 ;;   ult a5,a3,a0##ty=i64
 ;;   trap_if a5,heap_oob
@@ -49,7 +49,7 @@
 ;;   ugt a6,a3,a5##ty=i64
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   ld a7,[const(0)]
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
@@ -66,7 +66,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
+;;   ld a4,[const(1)]
 ;;   add a3,a0,a4
 ;;   ult a5,a3,a0##ty=i64
 ;;   trap_if a5,heap_oob
@@ -74,7 +74,7 @@
 ;;   ugt a6,a3,a5##ty=i64
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   ld a7,[const(0)]
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 46030e9bcb2d..8cc42340d0df 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
+;;   ld a4,[const(1)]
 ;;   add a3,a0,a4
 ;;   ult a5,a3,a0##ty=i64
 ;;   trap_if a5,heap_oob
@@ -49,7 +49,7 @@
 ;;   ugt a6,a3,a5##ty=i64
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   ld a7,[const(0)]
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
@@ -66,7 +66,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
+;;   ld a4,[const(1)]
 ;;   add a3,a0,a4
 ;;   ult a5,a3,a0##ty=i64
 ;;   trap_if a5,heap_oob
@@ -74,7 +74,7 @@
 ;;   ugt a6,a3,a5##ty=i64
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   ld a7,[const(0)]
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index b76521a575eb..6610e19f3235 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;; block1:
 ;;   ld a7,0(a2)
 ;;   add a7,a7,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0000
+;;   ld t3,[const(0)]
 ;;   add a7,a7,t3
 ;;   sw a1,0(a7)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; block1:
 ;;   ld a7,0(a1)
 ;;   add a7,a7,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0000
+;;   ld t3,[const(0)]
 ;;   add a7,a7,t3
 ;;   lw a0,0(a7)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 08213f990617..fa33426e1f66 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;; block1:
 ;;   ld a7,0(a2)
 ;;   add a7,a7,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0000
+;;   ld t3,[const(0)]
 ;;   add a7,a7,t3
 ;;   sb a1,0(a7)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; block1:
 ;;   ld a7,0(a1)
 ;;   add a7,a7,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0000
+;;   ld t3,[const(0)]
 ;;   add a7,a7,t3
 ;;   lbu a0,0(a7)
 ;;   j label2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index fb3ee241fa6b..6aaf4b8195a1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,7 +45,7 @@
 ;;   ugt a3,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
+;;   ld a4,[const(0)]
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
@@ -66,7 +66,7 @@
 ;;   ugt a2,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
-;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   ld a3,[const(0)]
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ef2f55b8b21b..fe78263f544b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,7 +45,7 @@
 ;;   ugt a3,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
-;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
+;;   ld a4,[const(0)]
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
@@ -66,7 +66,7 @@
 ;;   ugt a2,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
-;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   ld a3,[const(0)]
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255