From 5a54c642822a986c49c925c7cfe6af3d95df33c2 Mon Sep 17 00:00:00 2001
From: Vulcain <vulcain.dev@icloud.com>
Date: Wed, 31 Jul 2024 11:46:34 +0200
Subject: [PATCH] winch aarch64 jmp_table

---
 winch/codegen/src/isa/aarch64/asm.rs  | 18 ++++++++++++++++++
 winch/codegen/src/isa/aarch64/masm.rs | 12 ++++++++++--
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs
index 40ec8a35d156..aaa0e5dcdd81 100644
--- a/winch/codegen/src/isa/aarch64/asm.rs
+++ b/winch/codegen/src/isa/aarch64/asm.rs
@@ -490,6 +490,24 @@ impl Assembler {
         });
     }
 
+    /// Emits a jump table sequence.
+    pub fn jmp_table(
+        &mut self,
+        targets: &[MachLabel],
+        default: MachLabel,
+        index: Reg,
+        tmp1: Reg,
+        tmp2: Reg,
+    ) {
+        self.emit(Inst::JTSequence {
+            default,
+            targets: Box::new(targets.to_vec()),
+            ridx: index.into(),
+            rtmp1: Writable::from_reg(tmp1.into()),
+            rtmp2: Writable::from_reg(tmp2.into()),
+        });
+    }
+
     /// Conditional Set sets the destination register to 1 if the condition
     /// is true, and otherwise sets it to 0.
     pub fn cset(&mut self, rd: Reg, cond: Cond) {
diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs
index 02909927c971..2014c5543617 100644
--- a/winch/codegen/src/isa/aarch64/masm.rs
+++ b/winch/codegen/src/isa/aarch64/masm.rs
@@ -603,8 +603,16 @@ impl Masm for MacroAssembler {
         todo!()
     }
 
-    fn jmp_table(&mut self, _targets: &[MachLabel], _index: Reg, _tmp: Reg) {
-        todo!()
+    fn jmp_table(&mut self, targets: &[MachLabel], index: Reg, tmp: Reg) {
+        // At least one default target.
+        assert!(targets.len() >= 1);
+        let max = targets.len() as u64 - 1;
+        self.asm.subs_ir(max, index, OperandSize::S64);
+        let default_index = max as usize;
+        let default = targets[default_index];
+        let rest = &targets[..default_index];
+        let tmp1 = regs::scratch();
+        self.asm.jmp_table(rest, default, index, tmp1, tmp);
     }
 
     fn trap(&mut self, _code: TrapCode) {