From 5db384cd762a34b1c39ecdea7e9e40b32f3d9991 Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Wed, 27 May 2020 09:00:07 -0700
Subject: [PATCH] Rename opcode: PMULLQ to VPMULLQ

---
 cranelift/codegen/meta/src/isa/x86/encodings.rs | 2 +-
 cranelift/codegen/meta/src/isa/x86/opcodes.rs   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs
index dec0b8784208..8afe4e400b2b 100644
--- a/cranelift/codegen/meta/src/isa/x86/encodings.rs
+++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs
@@ -2108,7 +2108,7 @@ fn define_simd(
     {
         e.enc_32_64_maybe_isap(
             x86_pmullq,
-            rec_evex_reg_vvvv_rm_128.opcodes(&PMULLQ).w(),
+            rec_evex_reg_vvvv_rm_128.opcodes(&VPMULLQ).w(),
             Some(use_avx512dq_simd), // TODO need an OR predicate to join with AVX512VL
         );
     }
diff --git a/cranelift/codegen/meta/src/isa/x86/opcodes.rs b/cranelift/codegen/meta/src/isa/x86/opcodes.rs
index 8a65553bcf12..c1d4fa0ef5a2 100644
--- a/cranelift/codegen/meta/src/isa/x86/opcodes.rs
+++ b/cranelift/codegen/meta/src/isa/x86/opcodes.rs
@@ -471,7 +471,7 @@ pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
 
 /// Multiply the packed quadword signed integers in xmm2 and xmm3/m128 and store the low 64
 /// bits of each product in xmm1 (AVX512VL/DQ). Requires an EVEX encoding.
-pub static PMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
+pub static VPMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
 
 /// Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers
 /// in xmm2/m128, and store the quadword results in xmm1 (SSE2).