diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index b08d3cd173f9..24e4ade82428 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -152,14 +152,17 @@ where let imm = MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16) .unwrap(); - self.emitted_insts.push(MInst::MovN { rd, imm, size }); + self.emitted_insts + .push((MInst::MovN { rd, imm, size }, false)); } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - self.emitted_insts.push(MInst::MovZ { rd, imm, size }); + self.emitted_insts + .push((MInst::MovZ { rd, imm, size }, false)); } } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - self.emitted_insts.push(MInst::MovK { rd, imm, size }); + self.emitted_insts + .push((MInst::MovK { rd, imm, size }, false)); } } } @@ -200,7 +203,7 @@ where } fn emit(&mut self, inst: &MInst) -> Unit { - self.emitted_insts.push(inst.clone()); + self.emitted_insts.push((inst.clone(), false)); } fn cond_br_zero(&mut self, reg: Reg) -> CondBrKind { diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 0a7363962702..a40679106aa2 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -469,6 +469,6 @@ where #[inline] fn emit(&mut self, inst: &MInst) -> Unit { - self.emitted_insts.push(inst.clone()); + self.emitted_insts.push((inst.clone(), false)); } } diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 1f1bcb32d506..c6bd7651b413 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -227,7 +227,7 @@ where fn emit(&mut self, inst: &MInst) -> Unit { for inst in inst.clone().mov_mitosis() { - self.emitted_insts.push(inst); + self.emitted_insts.push((inst, false)); } } diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index d7d1fae60a4f..369f3d1f6616 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -299,12 +299,12 @@ macro_rules! isle_prelude_methods { /// internally has a temporary reference to a machinst `LowerCtx`. pub(crate) struct IsleContext<'a, C: LowerCtx, F, I, const N: usize> where - [C::I; N]: smallvec::Array, + [(C::I, bool); N]: smallvec::Array, { pub lower_ctx: &'a mut C, pub flags: &'a F, pub isa_flags: &'a I, - pub emitted_insts: SmallVec<[C::I; N]>, + pub emitted_insts: SmallVec<[(C::I, bool); N]>, } /// Shared lowering code amongst all backends for doing ISLE-based lowering. @@ -323,7 +323,7 @@ pub(crate) fn lower_common( ) -> Result<(), ()> where C: LowerCtx, - [C::I; N]: smallvec::Array, + [(C::I, bool); N]: smallvec::Array, { // TODO: reuse the ISLE context across lowerings so we can reuse its // internal heap allocations. @@ -367,7 +367,7 @@ where renamer.add_rename(*temp, dst.to_reg(), *ty); } } - for inst in isle_ctx.emitted_insts.iter_mut() { + for (inst, _) in isle_ctx.emitted_insts.iter_mut() { map_regs(inst, &renamer); } @@ -387,8 +387,12 @@ where // Once everything is remapped we forward all emitted instructions to the // `lower_ctx`. Note that this happens after the synthetic mov's above in // case any of these instruction use those movs. - for inst in isle_ctx.emitted_insts { - lower_ctx.emit(inst); + for (inst, is_safepoint) in isle_ctx.emitted_insts { + if is_safepoint { + lower_ctx.emit_safepoint(inst); + } else { + lower_ctx.emit(inst); + } } Ok(())