x64: Register allocation failure with simd instructions

[alexcrichton]

I think that this is along the lines of #3160, but this input:

(module
  (type (;0;) (func))
  (func (;0;) (type 0)
    v128.const i32x4 0x00000000 0x00000000 0x00000000 0x00000000
    i64x2.extend_low_i32x4_u
    v128.const i32x4 0x00000000 0x00000000 0x00000000 0x00000000
    i64x2.mul
    i32x4.all_true
    i64.load offset=1 align=1
    drop
    unreachable)
  (func (;1;) (type 0)
    nop)
  (memory (;0;) 5613 17832))

yields:

$ cargo run -q reduce/test.wat --enable-all
 ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode_ShowWithRRU {{
  Entry block: 0
Block 0:
  (original IR block: block0)
  (instruction range: 0 .. 13)
  Inst 0:   movq    %rdi, %v0J
  Inst 1:   movq    %rsi, %v1J
  Inst 2:   movdqa  %v6V, %v7V
  Inst 3:   pxor    %v14V, %v14V
  Inst 4:   pcmpeqd %v7V, %v14V
  Inst 5:   ptest   %v14V, %v14V
  Inst 6:   setz    %v8Jb
  Inst 7:   movq    %v8J, %v9J
  Inst 8:   andq    $1, %v9J
  Inst 9:   movl    %v9Jl, %v10Jl
  Inst 10:   movq    36(%v0J), %v11J
  Inst 11:   movq    1(%v11J,%v10J,1), %v13J
  Inst 12:   ud2 unreachable
}}

Error: Analysis(EntryLiveinValues([v6V]))
thread '<unnamed>' panicked at 'register allocation: Analysis(EntryLiveinValues([v6V]))', cranelift/codegen/src/machinst/compile.rs:96:10
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace

[cfallin]

@jlb6740 could you take a look? It looks like the SIMD lowering is missing an instruction somewhere: the movdqa moves out of v6, but v6 is never set. I expect this is an issue with the i64x2.extend_low_i32x4_u based on the input.