From 5e133965ac17cd50fd823912a0cb9350945c39e9 Mon Sep 17 00:00:00 2001 From: YuYang Date: Wed, 8 Mar 2023 14:20:01 +0800 Subject: [PATCH 1/4] fix issue5952 --- cranelift/codegen/src/isa/riscv64/lower.isle | 4 +-- .../filetests/isa/riscv64/fcvt-small.clif | 28 +++++++++++++------ .../filetests/isa/riscv64/float.clif | 28 +++++++++++++------ .../filetests/runtests/issue5952.clif | 14 ++++++++++ 4 files changed, 56 insertions(+), 18 deletions(-) create mode 100644 cranelift/filetests/filetests/runtests/issue5952.clif diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle index b08d6558f640..148b870db674 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.isle +++ b/cranelift/codegen/src/isa/riscv64/lower.isle @@ -802,12 +802,12 @@ ;;;;; Rules for `fcvt_from_sint`;;;;;;;;; (rule (lower (has_type to (fcvt_from_sint v @ (value_type from)))) - (fpu_rr (int_convert_2_float_op from $true to) to v)) + (fpu_rr (int_convert_2_float_op from $true to) to (normalize_cmp_value from v (ExtendOp.Signed)))) ;;;;; Rules for `fcvt_from_uint`;;;;;;;;; (rule (lower (has_type to (fcvt_from_uint v @ (value_type from)))) - (fpu_rr (int_convert_2_float_op from $false to) to v)) + (fpu_rr (int_convert_2_float_op from $false to) to (normalize_cmp_value from v (ExtendOp.Zero)))) ;;;;; Rules for `symbol_value`;;;;;;;;; (rule diff --git a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif index eb1be5612382..e821e120f08b 100644 --- a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif +++ b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif @@ -10,12 +10,14 @@ block0(v0: i8): ; VCode: ; block0: -; fcvt.s.lu fa0,a0 +; andi t2,a0,255 +; fcvt.s.lu fa0,t2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.s.lu fa0, a0 +; andi t2, a0, 0xff +; fcvt.s.lu fa0, t2 ; ret function u0:0(i8) -> f64 { @@ -26,12 +28,14 @@ block0(v0: i8): ; VCode: ; block0: -; fcvt.d.lu fa0,a0 +; andi t2,a0,255 +; fcvt.d.lu fa0,t2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.d.lu fa0, a0 +; andi t2, a0, 0xff +; fcvt.d.lu fa0, t2 ; ret function u0:0(i16) -> f32 { @@ -42,12 +46,16 @@ block0(v0: i16): ; VCode: ; block0: -; fcvt.s.lu fa0,a0 +; slli t2,a0,48 +; srli a1,t2,48 +; fcvt.s.lu fa0,a1 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.s.lu fa0, a0 +; slli t2, a0, 0x30 +; srli a1, t2, 0x30 +; fcvt.s.lu fa0, a1 ; ret function u0:0(i16) -> f64 { @@ -58,12 +66,16 @@ block0(v0: i16): ; VCode: ; block0: -; fcvt.d.lu fa0,a0 +; slli t2,a0,48 +; srli a1,t2,48 +; fcvt.d.lu fa0,a1 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.d.lu fa0, a0 +; slli t2, a0, 0x30 +; srli a1, t2, 0x30 +; fcvt.d.lu fa0, a1 ; ret function u0:0(f32) -> i8 { diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif index aa11b4b29673..65df462294b1 100644 --- a/cranelift/filetests/filetests/isa/riscv64/float.clif +++ b/cranelift/filetests/filetests/isa/riscv64/float.clif @@ -1026,12 +1026,16 @@ block0(v0: i32): ; VCode: ; block0: -; fcvt.s.wu fa0,a0 +; slli t2,a0,32 +; srli a1,t2,32 +; fcvt.s.wu fa0,a1 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.s.wu fa0, a0 +; slli t2, a0, 0x20 +; srli a1, t2, 0x20 +; fcvt.s.wu fa0, a1 ; ret function %f42(i32) -> f32 { @@ -1042,12 +1046,14 @@ block0(v0: i32): ; VCode: ; block0: -; fcvt.s.w fa0,a0 +; sext.w t2,a0 +; fcvt.s.w fa0,t2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.s.w fa0, a0 +; sext.w t2, a0 +; fcvt.s.w fa0, t2 ; ret function %f43(i64) -> f32 { @@ -1090,12 +1096,16 @@ block0(v0: i32): ; VCode: ; block0: -; fcvt.d.wu fa0,a0 +; slli t2,a0,32 +; srli a1,t2,32 +; fcvt.d.wu fa0,a1 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; fcvt.d.wu fa0, a0 +; slli t2, a0, 0x20 +; srli a1, t2, 0x20 +; fcvt.d.wu fa0, a1 ; ret function %f46(i32) -> f64 { @@ -1106,12 +1116,14 @@ block0(v0: i32): ; VCode: ; block0: -; fcvt.d.w fa0,a0 +; sext.w t2,a0 +; fcvt.d.w fa0,t2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; .byte 0x53, 0x75, 0x05, 0xd2 +; sext.w t2, a0 +; .byte 0x53, 0xf5, 0x03, 0xd2 ; ret function %f47(i64) -> f64 { diff --git a/cranelift/filetests/filetests/runtests/issue5952.clif b/cranelift/filetests/filetests/runtests/issue5952.clif new file mode 100644 index 000000000000..64a4a8f39978 --- /dev/null +++ b/cranelift/filetests/filetests/runtests/issue5952.clif @@ -0,0 +1,14 @@ +test interpret +test run +target aarch64 +target x86_64 +target s390x +target riscv64 + +function %a(i16 uext) -> f32 { +block0(v0: i16): + v1 = fcvt_from_sint.f32 v0 + return v1 +} + +; run: %a(-12800) == -0x1.900000p13 \ No newline at end of file From 78d70749b7ee93ba0328525ddb3bc7f2a7064d42 Mon Sep 17 00:00:00 2001 From: YuYang Date: Wed, 8 Mar 2023 14:45:13 +0800 Subject: [PATCH 2/4] We should only extend i8 and i16 --- cranelift/codegen/src/isa/riscv64/inst.isle | 7 +++++ cranelift/codegen/src/isa/riscv64/lower.isle | 4 +-- .../filetests/isa/riscv64/float.clif | 28 ++++++------------- 3 files changed, 17 insertions(+), 22 deletions(-) diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle index 4cee85ed5d49..b162688749aa 100644 --- a/cranelift/codegen/src/isa/riscv64/inst.isle +++ b/cranelift/codegen/src/isa/riscv64/inst.isle @@ -2122,6 +2122,13 @@ (ones Reg (load_imm12 -1))) (value_reg (gen_select_reg (IntCC.Equal) zero input zero ones)))) +(decl normalize_fcvt_from_int (ValueRegs Type ExtendOp) ValueRegs) +(rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op) + (extend r op ty $I64)) +(rule 1 (normalize_fcvt_from_int r _ _) + r) + + ;; Bitwise-or the two registers that make up the 128-bit value, then recurse as ;; though it was a 64-bit value. (rule diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle index 148b870db674..502871444ea0 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.isle +++ b/cranelift/codegen/src/isa/riscv64/lower.isle @@ -802,12 +802,12 @@ ;;;;; Rules for `fcvt_from_sint`;;;;;;;;; (rule (lower (has_type to (fcvt_from_sint v @ (value_type from)))) - (fpu_rr (int_convert_2_float_op from $true to) to (normalize_cmp_value from v (ExtendOp.Signed)))) + (fpu_rr (int_convert_2_float_op from $true to) to (normalize_fcvt_from_int v from (ExtendOp.Signed)))) ;;;;; Rules for `fcvt_from_uint`;;;;;;;;; (rule (lower (has_type to (fcvt_from_uint v @ (value_type from)))) - (fpu_rr (int_convert_2_float_op from $false to) to (normalize_cmp_value from v (ExtendOp.Zero)))) + (fpu_rr (int_convert_2_float_op from $false to) to (normalize_fcvt_from_int v from (ExtendOp.Zero)))) ;;;;; Rules for `symbol_value`;;;;;;;;; (rule diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif index 65df462294b1..aa11b4b29673 100644 --- a/cranelift/filetests/filetests/isa/riscv64/float.clif +++ b/cranelift/filetests/filetests/isa/riscv64/float.clif @@ -1026,16 +1026,12 @@ block0(v0: i32): ; VCode: ; block0: -; slli t2,a0,32 -; srli a1,t2,32 -; fcvt.s.wu fa0,a1 +; fcvt.s.wu fa0,a0 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; slli t2, a0, 0x20 -; srli a1, t2, 0x20 -; fcvt.s.wu fa0, a1 +; fcvt.s.wu fa0, a0 ; ret function %f42(i32) -> f32 { @@ -1046,14 +1042,12 @@ block0(v0: i32): ; VCode: ; block0: -; sext.w t2,a0 -; fcvt.s.w fa0,t2 +; fcvt.s.w fa0,a0 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; sext.w t2, a0 -; fcvt.s.w fa0, t2 +; fcvt.s.w fa0, a0 ; ret function %f43(i64) -> f32 { @@ -1096,16 +1090,12 @@ block0(v0: i32): ; VCode: ; block0: -; slli t2,a0,32 -; srli a1,t2,32 -; fcvt.d.wu fa0,a1 +; fcvt.d.wu fa0,a0 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; slli t2, a0, 0x20 -; srli a1, t2, 0x20 -; fcvt.d.wu fa0, a1 +; fcvt.d.wu fa0, a0 ; ret function %f46(i32) -> f64 { @@ -1116,14 +1106,12 @@ block0(v0: i32): ; VCode: ; block0: -; sext.w t2,a0 -; fcvt.d.w fa0,t2 +; fcvt.d.w fa0,a0 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; sext.w t2, a0 -; .byte 0x53, 0xf5, 0x03, 0xd2 +; .byte 0x53, 0x75, 0x05, 0xd2 ; ret function %f47(i64) -> f64 { From 7c632157df0772f16c0fd965bfe329eb19835378 Mon Sep 17 00:00:00 2001 From: YuYang Date: Wed, 8 Mar 2023 14:49:06 +0800 Subject: [PATCH 3/4] remove extra space --- cranelift/codegen/src/isa/riscv64/lower.isle | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle index 502871444ea0..e66ae43acc67 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.isle +++ b/cranelift/codegen/src/isa/riscv64/lower.isle @@ -807,7 +807,7 @@ ;;;;; Rules for `fcvt_from_uint`;;;;;;;;; (rule (lower (has_type to (fcvt_from_uint v @ (value_type from)))) - (fpu_rr (int_convert_2_float_op from $false to) to (normalize_fcvt_from_int v from (ExtendOp.Zero)))) + (fpu_rr (int_convert_2_float_op from $false to) to (normalize_fcvt_from_int v from (ExtendOp.Zero)))) ;;;;; Rules for `symbol_value`;;;;;;;;; (rule From 15e1e427fb7ba401b4ef71d5eb2a647ade2849af Mon Sep 17 00:00:00 2001 From: YuYang Date: Fri, 10 Mar 2023 08:52:12 +0800 Subject: [PATCH 4/4] move some code --- cranelift/codegen/src/isa/riscv64/inst.isle | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle index b162688749aa..66a0d942af33 100644 --- a/cranelift/codegen/src/isa/riscv64/inst.isle +++ b/cranelift/codegen/src/isa/riscv64/inst.isle @@ -1925,6 +1925,12 @@ (rule (normalize_cmp_value $I64 r _) r) (rule (normalize_cmp_value $I128 r _) r) +(decl normalize_fcvt_from_int (ValueRegs Type ExtendOp) ValueRegs) +(rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op) + (extend r op ty $I64)) +(rule 1 (normalize_fcvt_from_int r _ _) + r) + ;; Convert a truthy value, possibly of more than one register (an ;; I128), to one register. If narrower than 64 bits, must have already ;; been masked (e.g. by `normalize_cmp_value`). @@ -2122,13 +2128,6 @@ (ones Reg (load_imm12 -1))) (value_reg (gen_select_reg (IntCC.Equal) zero input zero ones)))) -(decl normalize_fcvt_from_int (ValueRegs Type ExtendOp) ValueRegs) -(rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op) - (extend r op ty $I64)) -(rule 1 (normalize_fcvt_from_int r _ _) - r) - - ;; Bitwise-or the two registers that make up the 128-bit value, then recurse as ;; though it was a 64-bit value. (rule