From 57cff60ad97f4a1cd9a69961bdb4e7ce5255e342 Mon Sep 17 00:00:00 2001 From: Chris Fallin Date: Fri, 10 Mar 2023 15:23:02 -0800 Subject: [PATCH] Cranelift: aarch64: fix undefined dest reg in f32x4.splat case. One of the cases for a splat operation, as updated in #5370, wrote to a temp reg but then only conditionally transformed the temp into the final destination register. In another codepath, `rd` was left undefined. This causes a panic later when regalloc2 verifies SSA properties of its input (here, value not def'd before use). Fixes #5985. --- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 22 +++++++++++++------ .../filetests/isa/aarch64/issue-5985.clif | 20 +++++++++++++++++ 2 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 cranelift/filetests/filetests/isa/aarch64/issue-5985.clif diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 1d91d08983ea..6e8e602de2d5 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -416,22 +416,30 @@ impl Inst { size }] } else if let Some(imm) = widen_32_bit_pattern(pattern, lane_size) { - let tmp = alloc_tmp(types::I64X2); - let mut insts = smallvec![Inst::VecDupImm { - rd: tmp, - imm, - invert: false, - size: VectorSize::Size64x2, - }]; + let mut insts = smallvec![]; // TODO: Implement support for 64-bit scalar MOVI; we zero-extend the // lower 64 bits instead. if !size.is_128bits() { + let tmp = alloc_tmp(types::I64X2); + insts.push(Inst::VecDupImm { + rd: tmp, + imm, + invert: false, + size: VectorSize::Size64x2, + }); insts.push(Inst::FpuExtend { rd, rn: tmp.to_reg(), size: ScalarSize::Size64, }); + } else { + insts.push(Inst::VecDupImm { + rd, + imm, + invert: false, + size: VectorSize::Size64x2, + }); } insts diff --git a/cranelift/filetests/filetests/isa/aarch64/issue-5985.clif b/cranelift/filetests/filetests/isa/aarch64/issue-5985.clif new file mode 100644 index 000000000000..7c14c47743d8 --- /dev/null +++ b/cranelift/filetests/filetests/isa/aarch64/issue-5985.clif @@ -0,0 +1,20 @@ +test compile precise-output +target aarch64 + +function %a() -> f32x4 system_v { +block0: + v16 = f32const 0x1.fffe00p-126 + v25 = splat.f32x4 v16 + return v25 +} + +; VCode: +; block0: +; movi v0.2d, #72056494543077120 +; ret +; +; Disassembled: +; block0: ; offset 0x0 +; movi v0.2d, #0xffff0000ffff00 +; ret +