From d60e0eeee584e9ccd2ae4af1de8f7bbfd7cc08c3 Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 01:31:56 +0100 Subject: [PATCH 1/9] emit 32bit udiv --- .../codegen/src/isa/aarch64/inst/emit.rs | 12 ++++++---- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/lower.isle | 24 +++++++++++++++---- 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 8775da127a92..f6bcdb875f3c 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -728,7 +728,7 @@ impl MachInstEmit for Inst { rm, } => { debug_assert!(match alu_op { - ALUOp::SDiv | ALUOp::UDiv | ALUOp::SMulH | ALUOp::UMulH => + ALUOp::SMulH | ALUOp::UMulH => size == OperandSize::Size64, _ => true, }); @@ -749,12 +749,14 @@ impl MachInstEmit for Inst { ALUOp::AddS => 0b00101011_000, ALUOp::SubS => 0b01101011_000, ALUOp::SDiv => 0b10011010_110, - ALUOp::UDiv => 0b10011010_110, + ALUOp::UDiv => 0b00011010_110, ALUOp::RotR | ALUOp::Lsr | ALUOp::Asr | ALUOp::Lsl => 0b00011010_110, ALUOp::SMulH => 0b10011011_010, ALUOp::UMulH => 0b10011011_110, }; - let top11 = top11 | size.sf_bit() << 10; + + dbg!(alu_op); + let top11 = top11 | dbg!(size.sf_bit()) << 10; let bit15_10 = match alu_op { ALUOp::SDiv => 0b000011, ALUOp::UDiv => 0b000010, @@ -770,7 +772,9 @@ impl MachInstEmit for Inst { // indication that something is wrong. debug_assert_ne!(stack_reg(), rn); debug_assert_ne!(stack_reg(), rm); - sink.put4(enc_arith_rrr(top11, bit15_10, rd, rn, rm)); + let inst =enc_arith_rrr(top11, bit15_10, rd, rn, rm); + println!("inst {alu_op:?}: {inst:b}"); + sink.put4(inst); } &Inst::AluRRRR { alu_op, diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 0762fb796834..17c5ce0f6340 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -1234,6 +1234,7 @@ impl Inst { rn, rm, } => { + dbg!(alu_op, size); let op = op_name(alu_op); let rd = pretty_print_ireg(rd.to_reg(), size); let rn = pretty_print_ireg(rn, size); diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle index 8ff4655bcad6..3fd9c15edd18 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.isle +++ b/cranelift/codegen/src/isa/aarch64/lower.isle @@ -1028,13 +1028,27 @@ ;;;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; TODO: Add UDiv32 to implement 32-bit directly, rather -;; than extending the input. -;; ;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of ;; CLIF's `udiv` the check for zero needs to be manually performed. -(rule udiv (lower (has_type (fits_in_64 ty) (udiv x y))) - (a64_udiv $I64 (put_in_reg_zext64 x) (put_nonzero_in_reg_zext64 y))) +(rule udiv 1 (lower (has_type $I64 (udiv x y))) + (a64_udiv $I64 (put_in_reg x) (trap_if_zero_divisor (put_in_reg y)))) + +(rule udiv (lower (has_type (fits_in_32 ty) (udiv x y))) + (a64_udiv $I32 (put_in_reg x) (put_nonzero_in_reg y))) + +;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero. +(spec (put_nonzero_in_reg x) + (provide (= result (zero_ext 64 x))) + (require (not (= result #x0000000000000000)))) +(decl put_nonzero_in_reg (Value) Reg) +(rule -1 (put_nonzero_in_reg val) + (trap_if_zero_divisor (put_in_reg val))) + +;; Special case where if a `Value` is known to be nonzero we can trivially +;; move it into a register. +(rule (put_nonzero_in_reg (and (value_type ty) + (iconst (nonzero_u64_from_imm64 n)))) + (imm ty (ImmExtend.Zero) n)) ;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero. (spec (put_nonzero_in_reg_zext64 x) From 5e566b80e2da04950fd431fc03495a4263825141 Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 02:04:06 +0100 Subject: [PATCH 2/9] winch: aarch64 udiv/urem without extension --- tests/disas/winch/aarch64/i32_divu/const.wat | 8 ++-- .../disas/winch/aarch64/i32_divu/one_zero.wat | 8 ++-- tests/disas/winch/aarch64/i32_divu/params.wat | 8 ++-- tests/disas/winch/aarch64/i32_divu/signed.wat | 8 ++-- .../winch/aarch64/i32_divu/zero_zero.wat | 8 ++-- tests/disas/winch/aarch64/i32_remu/const.wat | 10 ++--- .../disas/winch/aarch64/i32_remu/one_zero.wat | 10 ++--- tests/disas/winch/aarch64/i32_remu/params.wat | 10 ++--- tests/disas/winch/aarch64/i32_remu/signed.wat | 10 ++--- .../winch/aarch64/i32_remu/zero_zero.wat | 10 ++--- winch/codegen/src/isa/aarch64/asm.rs | 43 ++++++++----------- 11 files changed, 54 insertions(+), 79 deletions(-) diff --git a/tests/disas/winch/aarch64/i32_divu/const.wat b/tests/disas/winch/aarch64/i32_divu/const.wat index 777d40c8ee78..37ef95e08466 100644 --- a/tests/disas/winch/aarch64/i32_divu/const.wat +++ b/tests/disas/winch/aarch64/i32_divu/const.wat @@ -22,13 +22,11 @@ ;; mov w0, w16 ;; mov x16, #0x14 ;; mov w1, w16 -;; cbz x0, #0x54 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x1, x1, x0 +;; cbz x0, #0x4c +;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 54: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 4c: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_divu/one_zero.wat b/tests/disas/winch/aarch64/i32_divu/one_zero.wat index 4b2887f1c7c6..aeb1ac0eaa64 100644 --- a/tests/disas/winch/aarch64/i32_divu/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_divu/one_zero.wat @@ -22,13 +22,11 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x54 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x1, x1, x0 +;; cbz x0, #0x4c +;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 54: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 4c: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_divu/params.wat b/tests/disas/winch/aarch64/i32_divu/params.wat index f47118cc1bd8..07cef22aa2e8 100644 --- a/tests/disas/winch/aarch64/i32_divu/params.wat +++ b/tests/disas/winch/aarch64/i32_divu/params.wat @@ -22,13 +22,11 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x54 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x1, x1, x0 +;; cbz x0, #0x4c +;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x18 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 54: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 4c: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_divu/signed.wat b/tests/disas/winch/aarch64/i32_divu/signed.wat index aa796a5cd616..5a9472885d97 100644 --- a/tests/disas/winch/aarch64/i32_divu/signed.wat +++ b/tests/disas/winch/aarch64/i32_divu/signed.wat @@ -22,13 +22,11 @@ ;; mov w0, w16 ;; orr x16, xzr, #0xffffffff ;; mov w1, w16 -;; cbz x0, #0x54 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x1, x1, x0 +;; cbz x0, #0x4c +;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 54: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 4c: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_divu/zero_zero.wat b/tests/disas/winch/aarch64/i32_divu/zero_zero.wat index e98e8115bc80..dec4c99aa756 100644 --- a/tests/disas/winch/aarch64/i32_divu/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_divu/zero_zero.wat @@ -22,13 +22,11 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x54 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x1, x1, x0 +;; cbz x0, #0x4c +;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 54: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 4c: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_remu/const.wat b/tests/disas/winch/aarch64/i32_remu/const.wat index 7b073a44a039..3fd15a758dd9 100644 --- a/tests/disas/winch/aarch64/i32_remu/const.wat +++ b/tests/disas/winch/aarch64/i32_remu/const.wat @@ -22,14 +22,12 @@ ;; mov w0, w16 ;; mov x16, #7 ;; mov w1, w16 -;; cbz x0, #0x58 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x16, x1, x0 -;; msub x1, x0, x16, x1 +;; cbz x0, #0x50 +;; 34: udiv w16, w1, w0 +;; msub w1, w0, w16, w1 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 58: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 50: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_remu/one_zero.wat b/tests/disas/winch/aarch64/i32_remu/one_zero.wat index 484229500d98..a2187ee5bfcf 100644 --- a/tests/disas/winch/aarch64/i32_remu/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_remu/one_zero.wat @@ -22,14 +22,12 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x58 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x16, x1, x0 -;; msub x1, x0, x16, x1 +;; cbz x0, #0x50 +;; 34: udiv w16, w1, w0 +;; msub w1, w0, w16, w1 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 58: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 50: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_remu/params.wat b/tests/disas/winch/aarch64/i32_remu/params.wat index d107b220b14f..8b6d73d315ec 100644 --- a/tests/disas/winch/aarch64/i32_remu/params.wat +++ b/tests/disas/winch/aarch64/i32_remu/params.wat @@ -22,14 +22,12 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x58 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x16, x1, x0 -;; msub x1, x0, x16, x1 +;; cbz x0, #0x50 +;; 34: udiv w16, w1, w0 +;; msub w1, w0, w16, w1 ;; mov w0, w1 ;; add sp, sp, #0x18 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 58: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 50: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_remu/signed.wat b/tests/disas/winch/aarch64/i32_remu/signed.wat index 9f205360ab15..e0e22864e5c9 100644 --- a/tests/disas/winch/aarch64/i32_remu/signed.wat +++ b/tests/disas/winch/aarch64/i32_remu/signed.wat @@ -22,14 +22,12 @@ ;; mov w0, w16 ;; orr x16, xzr, #0xffffffff ;; mov w1, w16 -;; cbz x0, #0x58 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x16, x1, x0 -;; msub x1, x0, x16, x1 +;; cbz x0, #0x50 +;; 34: udiv w16, w1, w0 +;; msub w1, w0, w16, w1 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 58: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 50: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/tests/disas/winch/aarch64/i32_remu/zero_zero.wat b/tests/disas/winch/aarch64/i32_remu/zero_zero.wat index 4b5b48b8d14a..7d8203b79f54 100644 --- a/tests/disas/winch/aarch64/i32_remu/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_remu/zero_zero.wat @@ -22,14 +22,12 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x58 -;; 34: mov w0, w0 -;; mov w1, w1 -;; udiv x16, x1, x0 -;; msub x1, x0, x16, x1 +;; cbz x0, #0x50 +;; 34: udiv w16, w1, w0 +;; msub w1, w0, w16, w1 ;; mov w0, w1 ;; add sp, sp, #0x10 ;; mov x28, sp ;; ldp x29, x30, [sp], #0x10 ;; ret -;; 58: .byte 0x1f, 0xc1, 0x00, 0x00 +;; 50: .byte 0x1f, 0xc1, 0x00, 0x00 diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index 6bbc4994ac34..6b082e439a79 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -436,19 +436,17 @@ impl Assembler { self.trapif(Cond::Vs, TrapCode::INTEGER_OVERFLOW); } - // `cranelift-codegen` doesn't support emitting u/sdiv for anything but I64, + // `cranelift-codegen` doesn't support emitting sdiv for anything but I64, // we therefore sign-extend the operand. // see: https://github.com/bytecodealliance/wasmtime/issues/9766 - if size == OperandSize::S32 { - let extend_kind = if kind == DivKind::Signed { - ExtendKind::I64Extend32S - } else { - ExtendKind::I64ExtendI32U - }; + let size = if size == OperandSize::S32 && kind == DivKind::Signed { + self.extend(divisor, writable!(divisor), ExtendKind::I64Extend32S); + self.extend(dividend, writable!(dividend), ExtendKind::I64Extend32S); + OperandSize::S64 + } else { + size + }; - self.extend(divisor, writable!(divisor), extend_kind); - self.extend(dividend, writable!(dividend), extend_kind); - } let op = match kind { DivKind::Signed => ALUOp::SDiv, @@ -460,7 +458,7 @@ impl Assembler { divisor, dividend, dest.map(Into::into), - OperandSize::S64, + size, ); } @@ -476,19 +474,16 @@ impl Assembler { // Check for division by 0 self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO); - // `cranelift-codegen` doesn't support emitting u/sdiv for anything but I64, + // `cranelift-codegen` doesn't support emitting sdiv for anything but I64, // we therefore sign-extend the operand. // see: https://github.com/bytecodealliance/wasmtime/issues/9766 - if size == OperandSize::S32 { - let extend_kind = if kind.is_signed() { - ExtendKind::I64Extend32S - } else { - ExtendKind::I64ExtendI32U - }; - - self.extend(divisor, writable!(divisor), extend_kind); - self.extend(dividend, writable!(dividend), extend_kind); - } + let size = if size == OperandSize::S32 && kind.is_signed() { + self.extend(divisor, writable!(divisor), ExtendKind::I64Extend32S); + self.extend(dividend, writable!(dividend), ExtendKind::I64Extend32S); + OperandSize::S64 + } else { + size + }; let op = match kind { RemKind::Signed => ALUOp::SDiv, @@ -501,7 +496,7 @@ impl Assembler { divisor, dividend, writable!(scratch.into()), - OperandSize::S64, + size, ); self.emit_alu_rrrr( @@ -510,7 +505,7 @@ impl Assembler { divisor, dest.map(Into::into), dividend, - OperandSize::S64, + size, ); } From 0950d685fe57d09b8857ec31eab1201a5fd26dca Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 02:05:45 +0100 Subject: [PATCH 3/9] remove stray dbg! --- cranelift/codegen/src/isa/aarch64/inst/emit.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index f6bcdb875f3c..d722ea8379b9 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -755,8 +755,7 @@ impl MachInstEmit for Inst { ALUOp::UMulH => 0b10011011_110, }; - dbg!(alu_op); - let top11 = top11 | dbg!(size.sf_bit()) << 10; + let top11 = top11 | size.sf_bit() << 10; let bit15_10 = match alu_op { ALUOp::SDiv => 0b000011, ALUOp::UDiv => 0b000010, From 46b0a9e8a40ccc02a57e7b2e6489421d62f1be79 Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 02:06:18 +0100 Subject: [PATCH 4/9] fmt --- cranelift/codegen/src/isa/aarch64/inst/emit.rs | 5 ++--- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 - winch/codegen/src/isa/aarch64/asm.rs | 17 ++--------------- 3 files changed, 4 insertions(+), 19 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index d722ea8379b9..e2e4c0204cba 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -728,8 +728,7 @@ impl MachInstEmit for Inst { rm, } => { debug_assert!(match alu_op { - ALUOp::SMulH | ALUOp::UMulH => - size == OperandSize::Size64, + ALUOp::SMulH | ALUOp::UMulH => size == OperandSize::Size64, _ => true, }); let top11 = match alu_op { @@ -771,7 +770,7 @@ impl MachInstEmit for Inst { // indication that something is wrong. debug_assert_ne!(stack_reg(), rn); debug_assert_ne!(stack_reg(), rm); - let inst =enc_arith_rrr(top11, bit15_10, rd, rn, rm); + let inst = enc_arith_rrr(top11, bit15_10, rd, rn, rm); println!("inst {alu_op:?}: {inst:b}"); sink.put4(inst); } diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 17c5ce0f6340..0762fb796834 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -1234,7 +1234,6 @@ impl Inst { rn, rm, } => { - dbg!(alu_op, size); let op = op_name(alu_op); let rd = pretty_print_ireg(rd.to_reg(), size); let rn = pretty_print_ireg(rn, size); diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index 6b082e439a79..5142c5d5fc6a 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -447,19 +447,12 @@ impl Assembler { size }; - let op = match kind { DivKind::Signed => ALUOp::SDiv, DivKind::Unsigned => ALUOp::UDiv, }; - self.emit_alu_rrr( - op, - divisor, - dividend, - dest.map(Into::into), - size, - ); + self.emit_alu_rrr(op, divisor, dividend, dest.map(Into::into), size); } /// Signed/unsigned remainder operation with three registers. @@ -491,13 +484,7 @@ impl Assembler { }; let scratch = regs::scratch(); - self.emit_alu_rrr( - op, - divisor, - dividend, - writable!(scratch.into()), - size, - ); + self.emit_alu_rrr(op, divisor, dividend, writable!(scratch.into()), size); self.emit_alu_rrrr( ALUOp3::MSub, From 1d2b3291cd9fcc903a69a0de54e2dd816743556b Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 02:25:21 +0100 Subject: [PATCH 5/9] remove println --- cranelift/codegen/src/isa/aarch64/inst/emit.rs | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index e2e4c0204cba..8e2534311557 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -770,9 +770,7 @@ impl MachInstEmit for Inst { // indication that something is wrong. debug_assert_ne!(stack_reg(), rn); debug_assert_ne!(stack_reg(), rm); - let inst = enc_arith_rrr(top11, bit15_10, rd, rn, rm); - println!("inst {alu_op:?}: {inst:b}"); - sink.put4(inst); + sink.put4(enc_arith_rrr(top11, bit15_10, rd, rn, rm)); } &Inst::AluRRRR { alu_op, From ec28731c4e8d33876fcceb7c483bc2a6f9b045a3 Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 02:30:49 +0100 Subject: [PATCH 6/9] fix formatting in ISLE --- cranelift/codegen/src/isa/aarch64/lower.isle | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle index 3fd9c15edd18..6b4eb858538d 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.isle +++ b/cranelift/codegen/src/isa/aarch64/lower.isle @@ -1031,7 +1031,7 @@ ;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of ;; CLIF's `udiv` the check for zero needs to be manually performed. (rule udiv 1 (lower (has_type $I64 (udiv x y))) - (a64_udiv $I64 (put_in_reg x) (trap_if_zero_divisor (put_in_reg y)))) + (a64_udiv $I64 (put_in_reg x) (trap_if_zero_divisor (put_in_reg y)))) (rule udiv (lower (has_type (fits_in_32 ty) (udiv x y))) (a64_udiv $I32 (put_in_reg x) (put_nonzero_in_reg y))) From 5ec60163c3ee026c87d94352958bbc40d65139cc Mon Sep 17 00:00:00 2001 From: adhoc Date: Thu, 12 Dec 2024 12:07:03 +0100 Subject: [PATCH 7/9] Sized TrapIf --- cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst.isle | 29 ++++++------- .../codegen/src/isa/aarch64/inst/emit.rs | 41 +++++++++++++++---- .../src/isa/aarch64/inst/emit_tests.rs | 18 ++++++++ cranelift/codegen/src/isa/aarch64/inst/mod.rs | 5 ++- .../codegen/src/isa/aarch64/inst/regs.rs | 12 ++++++ cranelift/codegen/src/isa/aarch64/lower.isle | 28 +++++++------ cranelift/codegen/src/machinst/buffer.rs | 1 + .../filetests/isa/aarch64/arithmetic.clif | 26 +++++------- tests/disas/winch/aarch64/i32_divs/const.wat | 2 +- .../disas/winch/aarch64/i32_divs/one_zero.wat | 2 +- .../disas/winch/aarch64/i32_divs/overflow.wat | 2 +- tests/disas/winch/aarch64/i32_divs/params.wat | 2 +- .../winch/aarch64/i32_divs/zero_zero.wat | 2 +- tests/disas/winch/aarch64/i32_divu/const.wat | 2 +- .../disas/winch/aarch64/i32_divu/one_zero.wat | 2 +- tests/disas/winch/aarch64/i32_divu/params.wat | 2 +- tests/disas/winch/aarch64/i32_divu/signed.wat | 2 +- .../winch/aarch64/i32_divu/zero_zero.wat | 2 +- tests/disas/winch/aarch64/i32_rems/const.wat | 2 +- .../disas/winch/aarch64/i32_rems/one_zero.wat | 2 +- .../disas/winch/aarch64/i32_rems/overflow.wat | 2 +- tests/disas/winch/aarch64/i32_rems/params.wat | 2 +- .../winch/aarch64/i32_rems/zero_zero.wat | 2 +- tests/disas/winch/aarch64/i32_remu/const.wat | 2 +- .../disas/winch/aarch64/i32_remu/one_zero.wat | 2 +- tests/disas/winch/aarch64/i32_remu/params.wat | 2 +- tests/disas/winch/aarch64/i32_remu/signed.wat | 2 +- .../winch/aarch64/i32_remu/zero_zero.wat | 2 +- winch/codegen/src/isa/aarch64/asm.rs | 8 ++-- winch/codegen/src/isa/aarch64/masm.rs | 2 +- 31 files changed, 133 insertions(+), 78 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 44c276d07e9f..596809db9247 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -488,6 +488,7 @@ impl ABIMachineSpec for AArch64MachineDeps { // Here `Lo` == "less than" when interpreting the two // operands as unsigned integers. kind: CondBrKind::Cond(Cond::Lo), + size: OperandSize::Size64, }); insts } diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle index f1b7cbdbe947..5bd662f974d4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst.isle +++ b/cranelift/codegen/src/isa/aarch64/inst.isle @@ -870,6 +870,7 @@ ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse ;; of this condition in a branch that skips the trap instruction.) (TrapIf + (size OperandSize) (kind CondBrKind) (trap_code TrapCode)) @@ -3506,7 +3507,7 @@ (side_effect (with_flags_side_effect flags (ConsumesFlags.ConsumesFlagsSideEffect - (MInst.TrapIf (cond_br_cond cond) trap_code))))) + (MInst.TrapIf (operand_size $I64) (cond_br_cond cond) trap_code))))) ;; Helpers for lowering `trapz` and `trapnz`. (type ZeroCond @@ -3526,7 +3527,7 @@ (let ((reg Reg (put_in_reg_zext64 val))) (side_effect (SideEffectNoResult.Inst - (MInst.TrapIf (zero_cond_to_cond_br zero_cond reg) trap_code))))) + (MInst.TrapIf (operand_size $I64) (zero_cond_to_cond_br zero_cond reg) trap_code))))) (rule -1 (trap_if_val zero_cond val @ (value_type $I128) trap_code) (let ((c ValueRegs (put_in_regs val)) @@ -3535,7 +3536,7 @@ (c_test Reg (orr $I64 c_lo c_hi))) (side_effect (SideEffectNoResult.Inst - (MInst.TrapIf (zero_cond_to_cond_br zero_cond c_test) trap_code))))) + (MInst.TrapIf (operand_size $I64) (zero_cond_to_cond_br zero_cond c_test) trap_code))))) ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -3659,9 +3660,9 @@ ;; Misc instruction helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(decl trap_if_zero_divisor (Reg) Reg) -(rule (trap_if_zero_divisor reg) - (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg) (trap_code_division_by_zero))))) +(decl trap_if_zero_divisor (Reg OperandSize) Reg) +(rule (trap_if_zero_divisor reg size) + (let ((_ Unit (emit (MInst.TrapIf size (cond_br_zero reg) (trap_code_division_by_zero))))) reg)) (decl size_from_ty (Type) OperandSize) @@ -3685,7 +3686,7 @@ (u8_into_uimm5 1) (nzcv false false false false) (Cond.Eq)))) - (_ Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs)) + (_ Unit (emit (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Vs)) (trap_code_integer_overflow)))) ) x)) @@ -3709,7 +3710,7 @@ (with_flags_reg producer (ConsumesFlags.ConsumesFlagsSideEffect - (MInst.TrapIf (cond_br_cond (Cond.Hs)) tc)))) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Hs)) tc)))) (decl sink_atomic_load (Inst) Reg) (rule (sink_atomic_load x @ (atomic_load _ addr)) @@ -4272,7 +4273,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp size src src) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Vs)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Vs)) (trap_code_bad_conversion_to_integer)) src)))) (value_regs_get r 0))) @@ -4285,7 +4286,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (ScalarSize.Size32) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Le)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4293,7 +4294,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (ScalarSize.Size64) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Le)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4301,7 +4302,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (scalar_size in_ty) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Lt)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Lt)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4309,7 +4310,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (scalar_size in_ty) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Le)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4319,7 +4320,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp size src max) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (cond_br_cond (Cond.Ge)) + (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Ge)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 8e2534311557..691c0b9a9edf 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -164,10 +164,21 @@ fn enc_cbr(op_31_24: u32, off_18_0: u32, op_4: u32, cond: u32) -> u32 { (op_31_24 << 24) | (off_18_0 << 5) | (op_4 << 4) | cond } -fn enc_conditional_br(taken: BranchTarget, kind: CondBrKind) -> u32 { +/// Set the size bit of an instruction. +fn enc_op_size(op: u32, size: OperandSize) -> u32 { + (op & !(1 << 31)) | (size.sf_bit() << 31) +} + +fn enc_conditional_br(taken: BranchTarget, kind: CondBrKind, size: OperandSize) -> u32 { match kind { - CondBrKind::Zero(reg) => enc_cmpbr(0b1_011010_0, taken.as_offset19_or_zero(), reg), - CondBrKind::NotZero(reg) => enc_cmpbr(0b1_011010_1, taken.as_offset19_or_zero(), reg), + CondBrKind::Zero(reg) => enc_op_size( + enc_cmpbr(0b0_011010_0, taken.as_offset19_or_zero(), reg), + size, + ), + CondBrKind::NotZero(reg) => enc_op_size( + enc_cmpbr(0b0_011010_1, taken.as_offset19_or_zero(), reg), + size, + ), CondBrKind::Cond(c) => enc_cbr(0b01010100, taken.as_offset19_or_zero(), 0b0, c.bits()), } } @@ -1613,6 +1624,7 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(again_label), CondBrKind::NotZero(x24), + OperandSize::Size64, )); sink.use_label_at_offset(br_offset, again_label, LabelUse::Branch19); } @@ -1690,6 +1702,7 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(out_label), CondBrKind::Cond(Cond::Ne), + OperandSize::Size64, )); sink.use_label_at_offset(br_out_offset, out_label, LabelUse::Branch19); @@ -1706,6 +1719,7 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(again_label), CondBrKind::NotZero(x24), + OperandSize::Size64, )); sink.use_label_at_offset(br_again_offset, again_label, LabelUse::Branch19); @@ -2814,6 +2828,7 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(else_label), CondBrKind::Cond(cond), + OperandSize::Size64, )); sink.use_label_at_offset(br_else_offset, else_label, LabelUse::Branch19); @@ -2999,10 +3014,11 @@ impl MachInstEmit for Inst { let cond_off = sink.cur_offset(); if let Some(l) = taken.as_label() { sink.use_label_at_offset(cond_off, l, LabelUse::Branch19); - let inverted = enc_conditional_br(taken, kind.invert()).to_le_bytes(); + let inverted = + enc_conditional_br(taken, kind.invert(), OperandSize::Size64).to_le_bytes(); sink.add_cond_branch(cond_off, cond_off + 4, l, &inverted[..]); } - sink.put4(enc_conditional_br(taken, kind)); + sink.put4(enc_conditional_br(taken, kind, OperandSize::Size64)); // Unconditional part next. let uncond_off = sink.cur_offset(); @@ -3037,11 +3053,15 @@ impl MachInstEmit for Inst { } sink.put4(enc_jump26(0b000101, not_taken.as_offset26_or_zero())); } - &Inst::TrapIf { kind, trap_code } => { + &Inst::TrapIf { + kind, + trap_code, + size, + } => { let label = sink.defer_trap(trap_code); // condbr KIND, LABEL let off = sink.cur_offset(); - sink.put4(enc_conditional_br(BranchTarget::Label(label), kind)); + sink.put4(enc_conditional_br(BranchTarget::Label(label), kind, size)); sink.use_label_at_offset(off, label, LabelUse::Branch19); } &Inst::IndirectBr { rn, .. } => { @@ -3087,8 +3107,11 @@ impl MachInstEmit for Inst { // the middle; we depend on hardcoded PC-rel addressing below. // Branch to default when condition code from prior comparison indicates. - let br = - enc_conditional_br(BranchTarget::Label(default), CondBrKind::Cond(Cond::Hs)); + let br = enc_conditional_br( + BranchTarget::Label(default), + CondBrKind::Cond(Cond::Hs), + OperandSize::Size64, + ); // No need to inform the sink's branch folding logic about this branch, because it // will not be merged with any other branch, flipped, or elided (it is not preceded diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index ecf7f6dca8b1..95019d28259f 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -5901,6 +5901,7 @@ fn test_aarch64_binemit() { insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::NotZero(xreg(8)), }, @@ -5909,6 +5910,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Zero(xreg(8)), }, @@ -5917,6 +5919,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ne), }, @@ -5925,6 +5928,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Eq), }, @@ -5933,6 +5937,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Lo), }, @@ -5941,6 +5946,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Hs), }, @@ -5949,6 +5955,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Pl), }, @@ -5957,6 +5964,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Mi), }, @@ -5965,6 +5973,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Vc), }, @@ -5973,6 +5982,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Vs), }, @@ -5981,6 +5991,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ls), }, @@ -5989,6 +6000,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Hi), }, @@ -5997,6 +6009,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Lt), }, @@ -6005,6 +6018,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ge), }, @@ -6013,6 +6027,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Le), }, @@ -6021,6 +6036,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Gt), }, @@ -6029,6 +6045,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Nv), }, @@ -6037,6 +6054,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { + size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Al), }, diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 0762fb796834..dab8182e74e8 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -2669,15 +2669,16 @@ impl Inst { &Inst::Brk => "brk #0".to_string(), &Inst::Udf { .. } => "udf #0xc11f".to_string(), &Inst::TrapIf { + size, ref kind, trap_code, } => match kind { &CondBrKind::Zero(reg) => { - let reg = pretty_print_reg(reg); + let reg = pretty_print_reg_sized(reg, size); format!("cbz {reg}, #trap={trap_code}") } &CondBrKind::NotZero(reg) => { - let reg = pretty_print_reg(reg); + let reg = pretty_print_reg_sized(reg, size); format!("cbnz {reg}, #trap={trap_code}") } &CondBrKind::Cond(c) => { diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index c79c4fedfc19..6655ef36eb82 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -179,6 +179,18 @@ pub fn pretty_print_reg(reg: Reg) -> String { show_reg(reg) } +fn show_reg_sized(reg: Reg, size: OperandSize) -> String { + match reg.class() { + RegClass::Int => show_ireg_sized(reg, size), + RegClass::Float => todo!(), + RegClass::Vector => unreachable!(), + } +} + +pub fn pretty_print_reg_sized(reg: Reg, size: OperandSize) -> String { + show_reg_sized(reg, size) +} + /// If `ireg` denotes an Int-classed reg, make a best-effort attempt to show /// its name at the 32-bit size. pub fn show_ireg_sized(reg: Reg, size: OperandSize) -> String { diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle index 6b4eb858538d..3b49b0e4c85f 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.isle +++ b/cranelift/codegen/src/isa/aarch64/lower.isle @@ -1030,33 +1030,35 @@ ;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of ;; CLIF's `udiv` the check for zero needs to be manually performed. + (rule udiv 1 (lower (has_type $I64 (udiv x y))) - (a64_udiv $I64 (put_in_reg x) (trap_if_zero_divisor (put_in_reg y)))) + (a64_udiv $I64 (put_in_reg x) (put_nonzero_in_reg y))) (rule udiv (lower (has_type (fits_in_32 ty) (udiv x y))) - (a64_udiv $I32 (put_in_reg x) (put_nonzero_in_reg y))) + (a64_udiv $I32 (put_in_reg_zext32 x) (put_nonzero_in_reg y))) +;; helpers for udiv: ;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero. -(spec (put_nonzero_in_reg x) - (provide (= result (zero_ext 64 x))) - (require (not (= result #x0000000000000000)))) (decl put_nonzero_in_reg (Value) Reg) -(rule -1 (put_nonzero_in_reg val) - (trap_if_zero_divisor (put_in_reg val))) ;; Special case where if a `Value` is known to be nonzero we can trivially ;; move it into a register. -(rule (put_nonzero_in_reg (and (value_type ty) - (iconst (nonzero_u64_from_imm64 n)))) +(rule (put_nonzero_in_reg (and (value_type ty) (iconst (nonzero_u64_from_imm64 n)))) (imm ty (ImmExtend.Zero) n)) -;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero. +(rule -1 (put_nonzero_in_reg (and (value_type $I64) val)) + (trap_if_zero_divisor (put_in_reg val) (operand_size $I64))) + +(rule -2 (put_nonzero_in_reg (and (value_type (fits_in_32 _)) val)) + (trap_if_zero_divisor (put_in_reg_zext32 val) (operand_size $I32))) + +;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero and extending it to 64 bits. (spec (put_nonzero_in_reg_zext64 x) (provide (= result (zero_ext 64 x))) (require (not (= result #x0000000000000000)))) (decl put_nonzero_in_reg_zext64 (Value) Reg) -(rule -1 (put_nonzero_in_reg_zext64 val) - (trap_if_zero_divisor (put_in_reg_zext64 val))) +(rule -1 (put_nonzero_in_reg_zext64 (and (value_type ty) val)) + (trap_if_zero_divisor (put_in_reg_zext64 val) (operand_size ty))) ;; Special case where if a `Value` is known to be nonzero we can trivially ;; move it into a register. @@ -1106,7 +1108,7 @@ (require (not (= #x0000000000000000 result)))) (decl put_nonzero_in_reg_sext64 (Value) Reg) (rule -1 (put_nonzero_in_reg_sext64 val) - (trap_if_zero_divisor (put_in_reg_sext64 val))) + (trap_if_zero_divisor (put_in_reg_sext64 val) (operand_size $I64))) ;; Note that this has a special case where if the `Value` is a constant that's ;; not zero we can skip the zero check. diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index f08a32011a39..f68f088f81c4 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -2154,6 +2154,7 @@ mod test { let mut buf2 = MachBuffer::new(); let mut state = Default::default(); let inst = Inst::TrapIf { + size: crate::isa::aarch64::inst::OperandSize::Size64, kind: CondBrKind::NotZero(xreg(0)), trap_code: TrapCode::STACK_OVERFLOW, }; diff --git a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif index 569b9daa3c88..3bd7a2440fac 100644 --- a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif +++ b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif @@ -266,18 +266,14 @@ block0(v0: i32, v1: i32): ; VCode: ; block0: -; mov w3, w0 -; mov w5, w1 -; cbz x5, #trap=int_divz -; udiv x0, x3, x5 +; cbz w1, #trap=int_divz +; udiv w0, w0, w1 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; mov w3, w0 -; mov w5, w1 -; cbz x5, #0x14 -; udiv x0, x3, x5 +; cbz w1, #0xc +; udiv w0, w0, w1 ; ret ; .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz @@ -290,16 +286,14 @@ block0(v0: i32): ; VCode: ; block0: -; mov w2, w0 -; movz w4, #2 -; udiv x0, x2, x4 +; movz w2, #2 +; udiv w0, w0, w2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 -; mov w2, w0 -; mov w4, #2 -; udiv x0, x2, x4 +; mov w2, #2 +; udiv w0, w0, w2 ; ret function %f16(i32, i32) -> i32 { @@ -337,7 +331,7 @@ block0(v0: i32, v1: i32): ; block0: ; mov w3, w0 ; mov w5, w1 -; cbz x5, #trap=int_divz +; cbz w5, #trap=int_divz ; udiv x8, x3, x5 ; msub x0, x8, x5, x3 ; ret @@ -346,7 +340,7 @@ block0(v0: i32, v1: i32): ; block0: ; offset 0x0 ; mov w3, w0 ; mov w5, w1 -; cbz x5, #0x18 +; cbz w5, #0x18 ; udiv x8, x3, x5 ; msub x0, x8, x5, x3 ; ret diff --git a/tests/disas/winch/aarch64/i32_divs/const.wat b/tests/disas/winch/aarch64/i32_divs/const.wat index 92a6d05d1964..508092ef2d2d 100644 --- a/tests/disas/winch/aarch64/i32_divs/const.wat +++ b/tests/disas/winch/aarch64/i32_divs/const.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0x14 ;; mov w1, w16 -;; cbz x0, #0x60 +;; cbz w0, #0x60 ;; 34: cmn w0, #1 ;; ccmp w1, #1, #0, eq ;; b.vs #0x64 diff --git a/tests/disas/winch/aarch64/i32_divs/one_zero.wat b/tests/disas/winch/aarch64/i32_divs/one_zero.wat index e70375c293fe..b1b8245448a6 100644 --- a/tests/disas/winch/aarch64/i32_divs/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_divs/one_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x60 +;; cbz w0, #0x60 ;; 34: cmn w0, #1 ;; ccmp w1, #1, #0, eq ;; b.vs #0x64 diff --git a/tests/disas/winch/aarch64/i32_divs/overflow.wat b/tests/disas/winch/aarch64/i32_divs/overflow.wat index 88fc9621abaa..96cf36d96bca 100644 --- a/tests/disas/winch/aarch64/i32_divs/overflow.wat +++ b/tests/disas/winch/aarch64/i32_divs/overflow.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0x80000000 ;; mov w1, w16 -;; cbz x0, #0x60 +;; cbz w0, #0x60 ;; 34: cmn w0, #1 ;; ccmp w1, #1, #0, eq ;; b.vs #0x64 diff --git a/tests/disas/winch/aarch64/i32_divs/params.wat b/tests/disas/winch/aarch64/i32_divs/params.wat index 0976a08b25a8..a2ac680d80c5 100644 --- a/tests/disas/winch/aarch64/i32_divs/params.wat +++ b/tests/disas/winch/aarch64/i32_divs/params.wat @@ -22,7 +22,7 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x60 +;; cbz w0, #0x60 ;; 34: cmn w0, #1 ;; ccmp w1, #1, #0, eq ;; b.vs #0x64 diff --git a/tests/disas/winch/aarch64/i32_divs/zero_zero.wat b/tests/disas/winch/aarch64/i32_divs/zero_zero.wat index ce02fce00605..85ab0616ab2a 100644 --- a/tests/disas/winch/aarch64/i32_divs/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_divs/zero_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x60 +;; cbz w0, #0x60 ;; 34: cmn w0, #1 ;; ccmp w1, #1, #0, eq ;; b.vs #0x64 diff --git a/tests/disas/winch/aarch64/i32_divu/const.wat b/tests/disas/winch/aarch64/i32_divu/const.wat index 37ef95e08466..33966ddf38a7 100644 --- a/tests/disas/winch/aarch64/i32_divu/const.wat +++ b/tests/disas/winch/aarch64/i32_divu/const.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0x14 ;; mov w1, w16 -;; cbz x0, #0x4c +;; cbz w0, #0x4c ;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 diff --git a/tests/disas/winch/aarch64/i32_divu/one_zero.wat b/tests/disas/winch/aarch64/i32_divu/one_zero.wat index aeb1ac0eaa64..5e77c1d7e434 100644 --- a/tests/disas/winch/aarch64/i32_divu/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_divu/one_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x4c +;; cbz w0, #0x4c ;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 diff --git a/tests/disas/winch/aarch64/i32_divu/params.wat b/tests/disas/winch/aarch64/i32_divu/params.wat index 07cef22aa2e8..917506f751b3 100644 --- a/tests/disas/winch/aarch64/i32_divu/params.wat +++ b/tests/disas/winch/aarch64/i32_divu/params.wat @@ -22,7 +22,7 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x4c +;; cbz w0, #0x4c ;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x18 diff --git a/tests/disas/winch/aarch64/i32_divu/signed.wat b/tests/disas/winch/aarch64/i32_divu/signed.wat index 5a9472885d97..497f20bd71f0 100644 --- a/tests/disas/winch/aarch64/i32_divu/signed.wat +++ b/tests/disas/winch/aarch64/i32_divu/signed.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; orr x16, xzr, #0xffffffff ;; mov w1, w16 -;; cbz x0, #0x4c +;; cbz w0, #0x4c ;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 diff --git a/tests/disas/winch/aarch64/i32_divu/zero_zero.wat b/tests/disas/winch/aarch64/i32_divu/zero_zero.wat index dec4c99aa756..ae6fb3fc7d05 100644 --- a/tests/disas/winch/aarch64/i32_divu/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_divu/zero_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x4c +;; cbz w0, #0x4c ;; 34: udiv w1, w1, w0 ;; mov w0, w1 ;; add sp, sp, #0x10 diff --git a/tests/disas/winch/aarch64/i32_rems/const.wat b/tests/disas/winch/aarch64/i32_rems/const.wat index b01e691bae13..75fe7e1ffe82 100644 --- a/tests/disas/winch/aarch64/i32_rems/const.wat +++ b/tests/disas/winch/aarch64/i32_rems/const.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #7 ;; mov w1, w16 -;; cbz x0, #0x58 +;; cbz w0, #0x58 ;; 34: sxtw x0, w0 ;; sxtw x1, w1 ;; sdiv x16, x1, x0 diff --git a/tests/disas/winch/aarch64/i32_rems/one_zero.wat b/tests/disas/winch/aarch64/i32_rems/one_zero.wat index d38495fedd4c..30f50c35f136 100644 --- a/tests/disas/winch/aarch64/i32_rems/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_rems/one_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x58 +;; cbz w0, #0x58 ;; 34: sxtw x0, w0 ;; sxtw x1, w1 ;; sdiv x16, x1, x0 diff --git a/tests/disas/winch/aarch64/i32_rems/overflow.wat b/tests/disas/winch/aarch64/i32_rems/overflow.wat index f16ef7bacc85..fbadf741fe0d 100644 --- a/tests/disas/winch/aarch64/i32_rems/overflow.wat +++ b/tests/disas/winch/aarch64/i32_rems/overflow.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0x80000000 ;; mov w1, w16 -;; cbz x0, #0x58 +;; cbz w0, #0x58 ;; 34: sxtw x0, w0 ;; sxtw x1, w1 ;; sdiv x16, x1, x0 diff --git a/tests/disas/winch/aarch64/i32_rems/params.wat b/tests/disas/winch/aarch64/i32_rems/params.wat index 84fc8b067816..bf1a2ab6d8d9 100644 --- a/tests/disas/winch/aarch64/i32_rems/params.wat +++ b/tests/disas/winch/aarch64/i32_rems/params.wat @@ -22,7 +22,7 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x58 +;; cbz w0, #0x58 ;; 34: sxtw x0, w0 ;; sxtw x1, w1 ;; sdiv x16, x1, x0 diff --git a/tests/disas/winch/aarch64/i32_rems/zero_zero.wat b/tests/disas/winch/aarch64/i32_rems/zero_zero.wat index d032f4340b24..a84a1c1d9551 100644 --- a/tests/disas/winch/aarch64/i32_rems/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_rems/zero_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x58 +;; cbz w0, #0x58 ;; 34: sxtw x0, w0 ;; sxtw x1, w1 ;; sdiv x16, x1, x0 diff --git a/tests/disas/winch/aarch64/i32_remu/const.wat b/tests/disas/winch/aarch64/i32_remu/const.wat index 3fd15a758dd9..ae5af597c156 100644 --- a/tests/disas/winch/aarch64/i32_remu/const.wat +++ b/tests/disas/winch/aarch64/i32_remu/const.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #7 ;; mov w1, w16 -;; cbz x0, #0x50 +;; cbz w0, #0x50 ;; 34: udiv w16, w1, w0 ;; msub w1, w0, w16, w1 ;; mov w0, w1 diff --git a/tests/disas/winch/aarch64/i32_remu/one_zero.wat b/tests/disas/winch/aarch64/i32_remu/one_zero.wat index a2187ee5bfcf..8a2fabcd9768 100644 --- a/tests/disas/winch/aarch64/i32_remu/one_zero.wat +++ b/tests/disas/winch/aarch64/i32_remu/one_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #1 ;; mov w1, w16 -;; cbz x0, #0x50 +;; cbz w0, #0x50 ;; 34: udiv w16, w1, w0 ;; msub w1, w0, w16, w1 ;; mov w0, w1 diff --git a/tests/disas/winch/aarch64/i32_remu/params.wat b/tests/disas/winch/aarch64/i32_remu/params.wat index 8b6d73d315ec..be3b57194165 100644 --- a/tests/disas/winch/aarch64/i32_remu/params.wat +++ b/tests/disas/winch/aarch64/i32_remu/params.wat @@ -22,7 +22,7 @@ ;; stur w3, [x28] ;; ldur w0, [x28] ;; ldur w1, [x28, #4] -;; cbz x0, #0x50 +;; cbz w0, #0x50 ;; 34: udiv w16, w1, w0 ;; msub w1, w0, w16, w1 ;; mov w0, w1 diff --git a/tests/disas/winch/aarch64/i32_remu/signed.wat b/tests/disas/winch/aarch64/i32_remu/signed.wat index e0e22864e5c9..5d631f337dc6 100644 --- a/tests/disas/winch/aarch64/i32_remu/signed.wat +++ b/tests/disas/winch/aarch64/i32_remu/signed.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; orr x16, xzr, #0xffffffff ;; mov w1, w16 -;; cbz x0, #0x50 +;; cbz w0, #0x50 ;; 34: udiv w16, w1, w0 ;; msub w1, w0, w16, w1 ;; mov w0, w1 diff --git a/tests/disas/winch/aarch64/i32_remu/zero_zero.wat b/tests/disas/winch/aarch64/i32_remu/zero_zero.wat index 7d8203b79f54..51854e10e2d6 100644 --- a/tests/disas/winch/aarch64/i32_remu/zero_zero.wat +++ b/tests/disas/winch/aarch64/i32_remu/zero_zero.wat @@ -22,7 +22,7 @@ ;; mov w0, w16 ;; mov x16, #0 ;; mov w1, w16 -;; cbz x0, #0x50 +;; cbz w0, #0x50 ;; 34: udiv w16, w1, w0 ;; msub w1, w0, w16, w1 ;; mov w0, w1 diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index 5142c5d5fc6a..6ac294493183 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -410,7 +410,7 @@ impl Assembler { size: OperandSize, ) { // Check for division by 0. - self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO); + self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO, size); // check for overflow if kind == DivKind::Signed { @@ -465,7 +465,7 @@ impl Assembler { size: OperandSize, ) { // Check for division by 0 - self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO); + self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO, size); // `cranelift-codegen` doesn't support emitting sdiv for anything but I64, // we therefore sign-extend the operand. @@ -864,14 +864,16 @@ impl Assembler { /// Conditional trap. pub fn trapif(&mut self, cc: Cond, code: TrapCode) { self.emit(Inst::TrapIf { + size: OperandSize::S64.into(), kind: CondBrKind::Cond(cc), trap_code: code, }); } /// Trap if `rn` is zero. - pub fn trapz(&mut self, rn: Reg, code: TrapCode) { + pub fn trapz(&mut self, rn: Reg, code: TrapCode, size: OperandSize) { self.emit(Inst::TrapIf { + size: size.into(), kind: CondBrKind::Zero(rn.into()), trap_code: code, }); diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index fa91909aba3a..f63ae6dc9dc3 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -698,7 +698,7 @@ impl Masm for MacroAssembler { } fn trapz(&mut self, src: Reg, code: TrapCode) { - self.asm.trapz(src, code); + self.asm.trapz(src, code, OperandSize::S64); } fn trapif(&mut self, cc: IntCmpKind, code: TrapCode) { From 56aa1d9e90583b646f7d36f5219f66a51ea07a95 Mon Sep 17 00:00:00 2001 From: ad hoc Date: Sun, 15 Dec 2024 10:12:52 +0100 Subject: [PATCH 8/9] move operand size into CondBrKind variant --- cranelift/codegen/src/isa/aarch64/abi.rs | 1 - cranelift/codegen/src/isa/aarch64/inst.isle | 39 +++++++++---------- .../codegen/src/isa/aarch64/inst/args.rs | 8 ++-- .../codegen/src/isa/aarch64/inst/emit.rs | 34 ++++++---------- .../src/isa/aarch64/inst/emit_tests.rs | 22 +---------- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 17 ++++---- cranelift/codegen/src/isa/aarch64/lower.isle | 4 +- .../codegen/src/isa/aarch64/lower/isle.rs | 8 ++-- cranelift/codegen/src/machinst/buffer.rs | 19 +++++---- winch/codegen/src/isa/aarch64/asm.rs | 5 +-- 10 files changed, 61 insertions(+), 96 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 596809db9247..44c276d07e9f 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -488,7 +488,6 @@ impl ABIMachineSpec for AArch64MachineDeps { // Here `Lo` == "less than" when interpreting the two // operands as unsigned integers. kind: CondBrKind::Cond(Cond::Lo), - size: OperandSize::Size64, }); insts } diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle index 5bd662f974d4..b6b6ca700cba 100644 --- a/cranelift/codegen/src/isa/aarch64/inst.isle +++ b/cranelift/codegen/src/isa/aarch64/inst.isle @@ -870,7 +870,6 @@ ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse ;; of this condition in a branch that skips the trap instruction.) (TrapIf - (size OperandSize) (kind CondBrKind) (trap_code TrapCode)) @@ -1993,10 +1992,10 @@ (decl nzcv (bool bool bool bool) NZCV) (extern constructor nzcv nzcv) -(decl cond_br_zero (Reg) CondBrKind) +(decl cond_br_zero (Reg OperandSize) CondBrKind) (extern constructor cond_br_zero cond_br_zero) -(decl cond_br_not_zero (Reg) CondBrKind) +(decl cond_br_not_zero (Reg OperandSize) CondBrKind) (extern constructor cond_br_not_zero cond_br_not_zero) (decl cond_br_cond (Cond) CondBrKind) @@ -3507,7 +3506,7 @@ (side_effect (with_flags_side_effect flags (ConsumesFlags.ConsumesFlagsSideEffect - (MInst.TrapIf (operand_size $I64) (cond_br_cond cond) trap_code))))) + (MInst.TrapIf (cond_br_cond cond) trap_code))))) ;; Helpers for lowering `trapz` and `trapnz`. (type ZeroCond @@ -3515,19 +3514,19 @@ Zero NonZero)) -(decl zero_cond_to_cond_br (ZeroCond Reg) CondBrKind) -(rule (zero_cond_to_cond_br (ZeroCond.Zero) reg) - (cond_br_zero reg)) +(decl zero_cond_to_cond_br (ZeroCond Reg OperandSize) CondBrKind) +(rule (zero_cond_to_cond_br (ZeroCond.Zero) reg size) + (cond_br_zero reg size)) -(rule (zero_cond_to_cond_br (ZeroCond.NonZero) reg) - (cond_br_not_zero reg)) +(rule (zero_cond_to_cond_br (ZeroCond.NonZero) reg size) + (cond_br_not_zero reg size)) (decl trap_if_val (ZeroCond Value TrapCode) InstOutput) (rule (trap_if_val zero_cond val @ (value_type (fits_in_64 _)) trap_code) (let ((reg Reg (put_in_reg_zext64 val))) (side_effect (SideEffectNoResult.Inst - (MInst.TrapIf (operand_size $I64) (zero_cond_to_cond_br zero_cond reg) trap_code))))) + (MInst.TrapIf (zero_cond_to_cond_br zero_cond reg (operand_size $I64)) trap_code))))) (rule -1 (trap_if_val zero_cond val @ (value_type $I128) trap_code) (let ((c ValueRegs (put_in_regs val)) @@ -3536,7 +3535,7 @@ (c_test Reg (orr $I64 c_lo c_hi))) (side_effect (SideEffectNoResult.Inst - (MInst.TrapIf (operand_size $I64) (zero_cond_to_cond_br zero_cond c_test) trap_code))))) + (MInst.TrapIf (zero_cond_to_cond_br zero_cond c_test (operand_size $I64)) trap_code))))) ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -3662,7 +3661,7 @@ (decl trap_if_zero_divisor (Reg OperandSize) Reg) (rule (trap_if_zero_divisor reg size) - (let ((_ Unit (emit (MInst.TrapIf size (cond_br_zero reg) (trap_code_division_by_zero))))) + (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg size ) (trap_code_division_by_zero))))) reg)) (decl size_from_ty (Type) OperandSize) @@ -3686,7 +3685,7 @@ (u8_into_uimm5 1) (nzcv false false false false) (Cond.Eq)))) - (_ Unit (emit (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Vs)) + (_ Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs)) (trap_code_integer_overflow)))) ) x)) @@ -3710,7 +3709,7 @@ (with_flags_reg producer (ConsumesFlags.ConsumesFlagsSideEffect - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Hs)) tc)))) + (MInst.TrapIf (cond_br_cond (Cond.Hs)) tc)))) (decl sink_atomic_load (Inst) Reg) (rule (sink_atomic_load x @ (atomic_load _ addr)) @@ -4273,7 +4272,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp size src src) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Vs)) + (MInst.TrapIf (cond_br_cond (Cond.Vs)) (trap_code_bad_conversion_to_integer)) src)))) (value_regs_get r 0))) @@ -4286,7 +4285,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (ScalarSize.Size32) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) + (MInst.TrapIf (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4294,7 +4293,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (ScalarSize.Size64) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) + (MInst.TrapIf (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4302,7 +4301,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (scalar_size in_ty) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Lt)) + (MInst.TrapIf (cond_br_cond (Cond.Lt)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4310,7 +4309,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp (scalar_size in_ty) src min) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Le)) + (MInst.TrapIf (cond_br_cond (Cond.Le)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) @@ -4320,7 +4319,7 @@ (let ((r ValueRegs (with_flags (fpu_cmp size src max) (ConsumesFlags.ConsumesFlagsReturnsReg - (MInst.TrapIf (operand_size $I64) (cond_br_cond (Cond.Ge)) + (MInst.TrapIf (cond_br_cond (Cond.Ge)) (trap_code_integer_overflow)) src)))) (value_regs_get r 0))) diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index 575ed00fa07d..5ad617ca2bed 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -233,9 +233,9 @@ impl Cond { #[derive(Clone, Copy, Debug)] pub enum CondBrKind { /// Condition: given register is zero. - Zero(Reg), + Zero(Reg, OperandSize), /// Condition: given register is nonzero. - NotZero(Reg), + NotZero(Reg, OperandSize), /// Condition: the given condition-code test is true. Cond(Cond), } @@ -244,8 +244,8 @@ impl CondBrKind { /// Return the inverted branch condition. pub fn invert(self) -> CondBrKind { match self { - CondBrKind::Zero(reg) => CondBrKind::NotZero(reg), - CondBrKind::NotZero(reg) => CondBrKind::Zero(reg), + CondBrKind::Zero(reg, size) => CondBrKind::NotZero(reg, size), + CondBrKind::NotZero(reg, size) => CondBrKind::Zero(reg, size), CondBrKind::Cond(c) => CondBrKind::Cond(c.invert()), } } diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 691c0b9a9edf..b6d4177f17a9 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -169,13 +169,13 @@ fn enc_op_size(op: u32, size: OperandSize) -> u32 { (op & !(1 << 31)) | (size.sf_bit() << 31) } -fn enc_conditional_br(taken: BranchTarget, kind: CondBrKind, size: OperandSize) -> u32 { +fn enc_conditional_br(taken: BranchTarget, kind: CondBrKind) -> u32 { match kind { - CondBrKind::Zero(reg) => enc_op_size( + CondBrKind::Zero(reg, size) => enc_op_size( enc_cmpbr(0b0_011010_0, taken.as_offset19_or_zero(), reg), size, ), - CondBrKind::NotZero(reg) => enc_op_size( + CondBrKind::NotZero(reg, size) => enc_op_size( enc_cmpbr(0b0_011010_1, taken.as_offset19_or_zero(), reg), size, ), @@ -1623,8 +1623,7 @@ impl MachInstEmit for Inst { let br_offset = sink.cur_offset(); sink.put4(enc_conditional_br( BranchTarget::Label(again_label), - CondBrKind::NotZero(x24), - OperandSize::Size64, + CondBrKind::NotZero(x24, OperandSize::Size64), )); sink.use_label_at_offset(br_offset, again_label, LabelUse::Branch19); } @@ -1702,7 +1701,6 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(out_label), CondBrKind::Cond(Cond::Ne), - OperandSize::Size64, )); sink.use_label_at_offset(br_out_offset, out_label, LabelUse::Branch19); @@ -1718,8 +1716,7 @@ impl MachInstEmit for Inst { let br_again_offset = sink.cur_offset(); sink.put4(enc_conditional_br( BranchTarget::Label(again_label), - CondBrKind::NotZero(x24), - OperandSize::Size64, + CondBrKind::NotZero(x24, OperandSize::Size64), )); sink.use_label_at_offset(br_again_offset, again_label, LabelUse::Branch19); @@ -2828,7 +2825,6 @@ impl MachInstEmit for Inst { sink.put4(enc_conditional_br( BranchTarget::Label(else_label), CondBrKind::Cond(cond), - OperandSize::Size64, )); sink.use_label_at_offset(br_else_offset, else_label, LabelUse::Branch19); @@ -3014,11 +3010,10 @@ impl MachInstEmit for Inst { let cond_off = sink.cur_offset(); if let Some(l) = taken.as_label() { sink.use_label_at_offset(cond_off, l, LabelUse::Branch19); - let inverted = - enc_conditional_br(taken, kind.invert(), OperandSize::Size64).to_le_bytes(); + let inverted = enc_conditional_br(taken, kind.invert()).to_le_bytes(); sink.add_cond_branch(cond_off, cond_off + 4, l, &inverted[..]); } - sink.put4(enc_conditional_br(taken, kind, OperandSize::Size64)); + sink.put4(enc_conditional_br(taken, kind)); // Unconditional part next. let uncond_off = sink.cur_offset(); @@ -3053,15 +3048,11 @@ impl MachInstEmit for Inst { } sink.put4(enc_jump26(0b000101, not_taken.as_offset26_or_zero())); } - &Inst::TrapIf { - kind, - trap_code, - size, - } => { + &Inst::TrapIf { kind, trap_code } => { let label = sink.defer_trap(trap_code); // condbr KIND, LABEL let off = sink.cur_offset(); - sink.put4(enc_conditional_br(BranchTarget::Label(label), kind, size)); + sink.put4(enc_conditional_br(BranchTarget::Label(label), kind)); sink.use_label_at_offset(off, label, LabelUse::Branch19); } &Inst::IndirectBr { rn, .. } => { @@ -3107,11 +3098,8 @@ impl MachInstEmit for Inst { // the middle; we depend on hardcoded PC-rel addressing below. // Branch to default when condition code from prior comparison indicates. - let br = enc_conditional_br( - BranchTarget::Label(default), - CondBrKind::Cond(Cond::Hs), - OperandSize::Size64, - ); + let br = + enc_conditional_br(BranchTarget::Label(default), CondBrKind::Cond(Cond::Hs)); // No need to inform the sink's branch folding logic about this branch, because it // will not be merged with any other branch, flipped, or elided (it is not preceded diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index 95019d28259f..67a6ec8d848e 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -5901,25 +5901,22 @@ fn test_aarch64_binemit() { insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, - kind: CondBrKind::NotZero(xreg(8)), + kind: CondBrKind::NotZero(xreg(8), OperandSize::Size64), }, "280000B51FC10000", "cbnz x8, #trap=stk_ovf", )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, - kind: CondBrKind::Zero(xreg(8)), + kind: CondBrKind::Zero(xreg(8), OperandSize::Size64), }, "280000B41FC10000", "cbz x8, #trap=stk_ovf", )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ne), }, @@ -5928,7 +5925,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Eq), }, @@ -5937,7 +5933,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Lo), }, @@ -5946,7 +5941,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Hs), }, @@ -5955,7 +5949,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Pl), }, @@ -5964,7 +5957,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Mi), }, @@ -5973,7 +5965,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Vc), }, @@ -5982,7 +5973,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Vs), }, @@ -5991,7 +5981,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ls), }, @@ -6000,7 +5989,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Hi), }, @@ -6009,7 +5997,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Lt), }, @@ -6018,7 +6005,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Ge), }, @@ -6027,7 +6013,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Le), }, @@ -6036,7 +6021,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Gt), }, @@ -6045,7 +6029,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Nv), }, @@ -6054,7 +6037,6 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - size: OperandSize::Size64, trap_code: TrapCode::STACK_OVERFLOW, kind: CondBrKind::Cond(Cond::Al), }, diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index dab8182e74e8..2c60b0b5069f 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -873,7 +873,7 @@ fn aarch64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) { } } Inst::CondBr { kind, .. } => match kind { - CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => collector.reg_use(rt), + CondBrKind::Zero(rt, _) | CondBrKind::NotZero(rt, _) => collector.reg_use(rt), CondBrKind::Cond(_) => {} }, Inst::TestBitAndBranch { rn, .. } => { @@ -886,7 +886,7 @@ fn aarch64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) { Inst::Brk => {} Inst::Udf { .. } => {} Inst::TrapIf { kind, .. } => match kind { - CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => collector.reg_use(rt), + CondBrKind::Zero(rt, _) | CondBrKind::NotZero(rt, _) => collector.reg_use(rt), CondBrKind::Cond(_) => {} }, Inst::Adr { rd, .. } | Inst::Adrp { rd, .. } => { @@ -2632,12 +2632,12 @@ impl Inst { let taken = taken.pretty_print(0); let not_taken = not_taken.pretty_print(0); match kind { - &CondBrKind::Zero(reg) => { - let reg = pretty_print_reg(reg); + &CondBrKind::Zero(reg, size) => { + let reg = pretty_print_reg_sized(reg, size); format!("cbz {reg}, {taken} ; b {not_taken}") } - &CondBrKind::NotZero(reg) => { - let reg = pretty_print_reg(reg); + &CondBrKind::NotZero(reg, size) => { + let reg = pretty_print_reg_sized(reg, size); format!("cbnz {reg}, {taken} ; b {not_taken}") } &CondBrKind::Cond(c) => { @@ -2669,15 +2669,14 @@ impl Inst { &Inst::Brk => "brk #0".to_string(), &Inst::Udf { .. } => "udf #0xc11f".to_string(), &Inst::TrapIf { - size, ref kind, trap_code, } => match kind { - &CondBrKind::Zero(reg) => { + &CondBrKind::Zero(reg, size) => { let reg = pretty_print_reg_sized(reg, size); format!("cbz {reg}, #trap={trap_code}") } - &CondBrKind::NotZero(reg) => { + &CondBrKind::NotZero(reg, size) => { let reg = pretty_print_reg_sized(reg, size); format!("cbnz {reg}, #trap={trap_code}") } diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle index 3b49b0e4c85f..cdaabc97823a 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.isle +++ b/cranelift/codegen/src/isa/aarch64/lower.isle @@ -3095,14 +3095,14 @@ (rt Reg (orr $I64 c_lo c_hi))) (emit_side_effect (with_flags_side_effect flags - (cond_br taken not_taken (cond_br_not_zero rt)))))) + (cond_br taken not_taken (cond_br_not_zero rt (operand_size $I64))))))) (rule -2 (lower_branch (brif c @ (value_type ty) _ _) (two_targets taken not_taken)) (if (ty_int_ref_scalar_64 ty)) (let ((flags ProducesFlags (flags_to_producesflags c)) (rt Reg (put_in_reg_zext64 c))) (emit_side_effect (with_flags_side_effect flags - (cond_br taken not_taken (cond_br_not_zero rt)))))) + (cond_br taken not_taken (cond_br_not_zero rt (operand_size $I64))))))) ;; Special lowerings for `tbnz` - "Test bit and Branch if Nonzero" (rule 1 (lower_branch (brif (band x @ (value_type ty) (u64_from_iconst n)) _ _) diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 0c05db4bc4ce..b9eb8eb531ea 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -354,12 +354,12 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.lower_ctx.emit(inst.clone()); } - fn cond_br_zero(&mut self, reg: Reg) -> CondBrKind { - CondBrKind::Zero(reg) + fn cond_br_zero(&mut self, reg: Reg, size: &OperandSize) -> CondBrKind { + CondBrKind::Zero(reg, *size) } - fn cond_br_not_zero(&mut self, reg: Reg) -> CondBrKind { - CondBrKind::NotZero(reg) + fn cond_br_not_zero(&mut self, reg: Reg, size: &OperandSize) -> CondBrKind { + CondBrKind::NotZero(reg, *size) } fn cond_br_cond(&mut self, cond: &Cond) -> CondBrKind { diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index f68f088f81c4..93c11658e34a 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -2061,7 +2061,7 @@ mod test { use super::*; use crate::ir::UserExternalNameRef; - use crate::isa::aarch64::inst::xreg; + use crate::isa::aarch64::inst::{xreg, OperandSize}; use crate::isa::aarch64::inst::{BranchTarget, CondBrKind, EmitInfo, Inst}; use crate::machinst::{MachInstEmit, MachInstEmitState}; use crate::settings; @@ -2100,7 +2100,7 @@ mod test { buf.bind_label(label(0), state.ctrl_plane_mut()); let inst = Inst::CondBr { - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), taken: target(1), not_taken: target(2), }; @@ -2131,7 +2131,7 @@ mod test { buf.bind_label(label(0), state.ctrl_plane_mut()); let inst = Inst::CondBr { - kind: CondBrKind::Zero(xreg(0)), + kind: CondBrKind::Zero(xreg(0), OperandSize::Size64), taken: target(1), not_taken: target(2), }; @@ -2154,8 +2154,7 @@ mod test { let mut buf2 = MachBuffer::new(); let mut state = Default::default(); let inst = Inst::TrapIf { - size: crate::isa::aarch64::inst::OperandSize::Size64, - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), trap_code: TrapCode::STACK_OVERFLOW, }; inst.emit(&mut buf2, &info, &mut state); @@ -2178,7 +2177,7 @@ mod test { buf.bind_label(label(0), state.ctrl_plane_mut()); let inst = Inst::CondBr { - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), taken: target(2), not_taken: target(3), }; @@ -2208,7 +2207,7 @@ mod test { let mut buf2 = MachBuffer::new(); let mut state = Default::default(); let inst = Inst::CondBr { - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), // This conditionally taken branch has a 19-bit constant, shifted // to the left by two, giving us a 21-bit range in total. Half of @@ -2261,7 +2260,7 @@ mod test { buf.bind_label(label(3), state.ctrl_plane_mut()); let inst = Inst::CondBr { - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), taken: target(0), not_taken: target(1), }; @@ -2274,7 +2273,7 @@ mod test { let mut buf2 = MachBuffer::new(); let mut state = Default::default(); let inst = Inst::CondBr { - kind: CondBrKind::NotZero(xreg(0)), + kind: CondBrKind::NotZero(xreg(0), OperandSize::Size64), taken: BranchTarget::ResolvedOffset(8), not_taken: BranchTarget::ResolvedOffset(4 - (2000000 + 4)), }; @@ -2333,7 +2332,7 @@ mod test { buf.bind_label(label(0), state.ctrl_plane_mut()); let inst = Inst::CondBr { - kind: CondBrKind::Zero(xreg(0)), + kind: CondBrKind::Zero(xreg(0), OperandSize::Size64), taken: target(1), not_taken: target(2), }; diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index 6ac294493183..76797581f849 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -10,6 +10,7 @@ use crate::{ masm::OperandSize, reg::{writable, Reg, WritableReg}, }; + use cranelift_codegen::isa::aarch64::inst::{UImm5, NZCV}; use cranelift_codegen::{ ir::{ExternalName, LibCall, MemFlags, SourceLoc, TrapCode, UserExternalNameRef}, @@ -864,7 +865,6 @@ impl Assembler { /// Conditional trap. pub fn trapif(&mut self, cc: Cond, code: TrapCode) { self.emit(Inst::TrapIf { - size: OperandSize::S64.into(), kind: CondBrKind::Cond(cc), trap_code: code, }); @@ -873,8 +873,7 @@ impl Assembler { /// Trap if `rn` is zero. pub fn trapz(&mut self, rn: Reg, code: TrapCode, size: OperandSize) { self.emit(Inst::TrapIf { - size: size.into(), - kind: CondBrKind::Zero(rn.into()), + kind: CondBrKind::Zero(rn.into(), size.into()), trap_code: code, }); } From c9577d86f11db7d221a0009e3faf955a231bc522 Mon Sep 17 00:00:00 2001 From: ad hoc Date: Sun, 15 Dec 2024 10:22:52 +0100 Subject: [PATCH 9/9] show_reg_sized fallback --- cranelift/codegen/src/isa/aarch64/inst/regs.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 6655ef36eb82..fd1abb7fffb4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -182,7 +182,7 @@ pub fn pretty_print_reg(reg: Reg) -> String { fn show_reg_sized(reg: Reg, size: OperandSize) -> String { match reg.class() { RegClass::Int => show_ireg_sized(reg, size), - RegClass::Float => todo!(), + RegClass::Float => show_reg(reg), RegClass::Vector => unreachable!(), } }