diff --git a/spydrnet/parsers/verilog/parser.py b/spydrnet/parsers/verilog/parser.py
index 7140615f..ceafd38f 100644
--- a/spydrnet/parsers/verilog/parser.py
+++ b/spydrnet/parsers/verilog/parser.py
@@ -1397,13 +1397,13 @@ def create_assignment_instance(self, width):
         instance.reference = definition
         return instance
 
-    def connect_wires_for_assign(self, out_wires, in_wires
-        # self, l_cable, l_left, l_right, r_cable, r_left, r_right
+    def connect_wires_for_assign(
+        self, l_cable, l_left, l_right, r_cable, r_left, r_right
     ):
         """connect the wires in r_left to the wires in l_left"""
 
-        # out_wires = self.get_wires_from_cable(l_cable, l_left, l_right)
-        # in_wires = self.get_wires_from_cable(r_cable, r_left, r_right)
+        out_wires = self.get_wires_from_cable(l_cable, l_left, l_right)
+        in_wires = self.get_wires_from_cable(r_cable, r_left, r_right)
 
         # min because we don't need extra pins since only what can will assign.
         width = min(len(out_wires), len(in_wires))
diff --git a/tests/spydrnet/parsers/verilog/tests/test_verilogParser.py b/tests/spydrnet/parsers/verilog/tests/test_verilogParser.py
index 2f3183c5..adb57704 100644
--- a/tests/spydrnet/parsers/verilog/tests/test_verilogParser.py
+++ b/tests/spydrnet/parsers/verilog/tests/test_verilogParser.py
@@ -1607,9 +1607,7 @@ def test_connect_assigned_wires(self):
         i_cable = parser.current_definition.create_cable(name="c2")
         o_cable.create_wires(4)
         i_cable.create_wires(4)
-        l_wires = parser.get_wires_from_cable(o_cable, 1, 0)
-        r_wires = parser.get_wires_from_cable(i_cable, 3, 2)
-        parser.connect_wires_for_assign(l_wires, r_wires)
+        parser.connect_wires_for_assign(o_cable, 1, 0, i_cable, 3, 2)
 
         instance = next(parser.current_definition.get_instances("SDN_VERILOG_ASSIGNMENT*"))
         for pin in instance.pins: